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[Modified] pre submit file organization

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包焕垲
2023-08-04 16:10:30 +08:00
parent df11c3a4ab
commit f87199d467
35 changed files with 98 additions and 5939 deletions
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406
lacpu/rtl/mycpu/cache_data.v
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@@ -65,7 +65,7 @@ module cache_data_v5
data_bram_bank bank0_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[0]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[31:0]:sram_wdata ), // 32
.douta (rdata_way0[0] ) // 32
@@ -73,7 +73,7 @@ module cache_data_v5
data_bram_bank bank1_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[1]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[63:32]:sram_wdata ), // 32
.douta (rdata_way0[1] ) // 32
@@ -81,7 +81,7 @@ module cache_data_v5
data_bram_bank bank2_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[2]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[95:64]:sram_wdata ), // 32
.douta (rdata_way0[2] ) // 32
@@ -89,7 +89,7 @@ module cache_data_v5
data_bram_bank bank3_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[3]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[127:96]:sram_wdata ), // 32
.douta (rdata_way0[3] ) // 32
@@ -97,7 +97,7 @@ module cache_data_v5
data_bram_bank bank4_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[4]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[159:128]:sram_wdata ), // 32
.douta (rdata_way0[4] ) // 32
@@ -105,7 +105,7 @@ module cache_data_v5
data_bram_bank bank5_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[5]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[191:160]:sram_wdata ), // 32
.douta (rdata_way0[5] ) // 32
@@ -113,7 +113,7 @@ module cache_data_v5
data_bram_bank bank6_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[6]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[223:192]:sram_wdata ), // 32
.douta (rdata_way0[6] ) // 32
@@ -121,7 +121,7 @@ module cache_data_v5
data_bram_bank bank7_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[7]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[255:224]:sram_wdata ), // 32
.douta (rdata_way0[7] ) // 32
@@ -399,394 +399,4 @@ module cache_data_v5
};
assign cacheline_old = lru_r ? cacheline_old_way1 : cacheline_old_way0;
endmodule
module cache_data_v6
#(
parameter CACHELINE_WD = 512,
parameter TAG_WD = 21,
parameter HIT_WD = 2
)
(
input clk,
input reset,
input write_back,
input [ 1:0] hit,
input lru,
input cached,
// sram_port
input sram_en,
input [ 3:0] sram_we,
input [31:0] sram_addr,
input [31:0] sram_wdata,
output [63:0] sram_rdata,
// axi
input refresh,
input [CACHELINE_WD -1:0] cacheline_new,
output [CACHELINE_WD -1:0] cacheline_old
);
wire [31 :0] rdata_way0 [15:0];
wire [31 :0] rdata_way1 [15:0];
wire [TAG_WD -2:0] tag;
wire [5 :0] index;
wire [5 :0] offset;
reg [HIT_WD- 1:0] hit_r;
reg lru_r;
reg cached_r;
assign {tag,
index,
offset
} = sram_addr;
wire [15:0] bank_sel;
reg [15:0] bank_sel_r;
decoder_4_16 u_decoder_4_16(
.in (offset[5:2] ),
.out (bank_sel )
);
always @ (posedge clk) begin
if (reset) begin
hit_r <= 2'b0;
lru_r <= 1'b0;
cached_r <= 1'b1;
bank_sel_r <= 16'b0;
end
else begin
hit_r <= hit;
lru_r <= lru;
cached_r <= cached;
bank_sel_r <= bank_sel;
end
end
// data_bram_way0 begin
data_bram_bank bank0_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[0]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[31:0]:sram_wdata ), // 32
.douta (rdata_way0[0] ) // 32
);
data_bram_bank bank1_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[0]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[63:32]:sram_wdata ), // 32
.douta (rdata_way0[1] ) // 32
);
data_bram_bank bank2_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[2]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[95:64]:sram_wdata ), // 32
.douta (rdata_way0[2] ) // 32
);
data_bram_bank bank3_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[2]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[127:96]:sram_wdata ), // 32
.douta (rdata_way0[3] ) // 32
);
data_bram_bank bank4_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[4]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[159:128]:sram_wdata ), // 32
.douta (rdata_way0[4] ) // 32
);
data_bram_bank bank5_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[4]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[191:160]:sram_wdata ), // 32
.douta (rdata_way0[5] ) // 32
);
data_bram_bank bank6_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[6]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[223:192]:sram_wdata ), // 32
.douta (rdata_way0[6] ) // 32
);
data_bram_bank bank7_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[6]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[255:224]:sram_wdata ), // 32
.douta (rdata_way0[7] ) // 32
);
data_bram_bank bank8_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[8]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[287:256]:sram_wdata ), // 32
.douta (rdata_way0[8] ) // 32
);
data_bram_bank bank9_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[8]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[319:288]:sram_wdata ), // 32
.douta (rdata_way0[9] ) // 32
);
data_bram_bank bank10_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[10]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[351:320]:sram_wdata ), // 32
.douta (rdata_way0[10] ) // 32
);
data_bram_bank bank11_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[10]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[383:352]:sram_wdata ), // 32
.douta (rdata_way0[11] ) // 32
);
data_bram_bank bank12_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[12]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[415:384]:sram_wdata ), // 32
.douta (rdata_way0[12] ) // 32
);
data_bram_bank bank13_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[12]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[447:416]:sram_wdata ), // 32
.douta (rdata_way0[13] ) // 32
);
data_bram_bank bank14_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[14]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[479:448]:sram_wdata ), // 32
.douta (rdata_way0[14] ) // 32
);
data_bram_bank bank15_way0(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[14]&hit[0]|write_back ), // 1
.wea (refresh?lru?4'b0000:4'b1111:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[511:480]:sram_wdata ), // 32
.douta (rdata_way0[15] ) // 32
);
// data_bram_way0 end
// data_bram_way1 begin
data_bram_bank bank0_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[0]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[31:0]:sram_wdata ), // 32
.douta (rdata_way1[0] ) // 32
);
data_bram_bank bank1_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[0]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[63:32]:sram_wdata ), // 32
.douta (rdata_way1[1] ) // 32
);
data_bram_bank bank2_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[2]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[95:64]:sram_wdata ), // 32
.douta (rdata_way1[2] ) // 32
);
data_bram_bank bank3_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[2]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[127:96]:sram_wdata ), // 32
.douta (rdata_way1[3] ) // 32
);
data_bram_bank bank4_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[4]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[159:128]:sram_wdata ), // 32
.douta (rdata_way1[4] ) // 32
);
data_bram_bank bank5_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[4]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[191:160]:sram_wdata ), // 32
.douta (rdata_way1[5] ) // 32
);
data_bram_bank bank6_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[6]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[223:192]:sram_wdata ), // 32
.douta (rdata_way1[6] ) // 32
);
data_bram_bank bank7_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[6]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[255:224]:sram_wdata ), // 32
.douta (rdata_way1[7] ) // 32
);
data_bram_bank bank8_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[8]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[287:256]:sram_wdata ), // 32
.douta (rdata_way1[8] ) // 32
);
data_bram_bank bank9_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[8]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[319:288]:sram_wdata ), // 32
.douta (rdata_way1[9] ) // 32
);
data_bram_bank bank10_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[10]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[351:320]:sram_wdata ), // 32
.douta (rdata_way1[10] ) // 32
);
data_bram_bank bank11_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[10]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[383:352]:sram_wdata ), // 32
.douta (rdata_way1[11] ) // 32
);
data_bram_bank bank12_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[12]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[415:384]:sram_wdata ), // 32
.douta (rdata_way1[12] ) // 32
);
data_bram_bank bank13_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[12]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[447:416]:sram_wdata ), // 32
.douta (rdata_way1[13] ) // 32
);
data_bram_bank bank14_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[14]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[479:448]:sram_wdata ), // 32
.douta (rdata_way1[14] ) // 32
);
data_bram_bank bank15_way1(
.clka (clk ),
.ena (cached&refresh|sram_en&bank_sel[14]&hit[1]|write_back ), // 1
.wea (refresh?lru?4'b1111:4'b0000:write_back?4'b0000:sram_we), // 4
.addra (index ), // 7
.dina (refresh?cacheline_new[511:480]:sram_wdata ), // 32
.douta (rdata_way1[15] ) // 32
);
// data_bram_way1 end
wire [63:0] sram_rdata_way0,sram_rdata_way1;
assign sram_rdata_way0 = ~cached_r ? 64'b0 :
bank_sel_r[ 0] ? {rdata_way0[ 1],rdata_way0[ 0]} :
bank_sel_r[ 2] ? {rdata_way0[ 3],rdata_way0[ 2]} :
bank_sel_r[ 4] ? {rdata_way0[ 5],rdata_way0[ 4]} :
bank_sel_r[ 6] ? {rdata_way0[ 7],rdata_way0[ 6]} :
bank_sel_r[ 8] ? {rdata_way0[ 9],rdata_way0[ 8]} :
bank_sel_r[10] ? {rdata_way0[11],rdata_way0[10]} :
bank_sel_r[12] ? {rdata_way0[13],rdata_way0[12]} :
bank_sel_r[14] ? {rdata_way0[15],rdata_way0[14]} : 64'b0;
assign sram_rdata_way1 = ~cached_r ? 64'b0 :
bank_sel_r[ 0] ? {rdata_way1[ 1],rdata_way1[ 0]} :
bank_sel_r[ 2] ? {rdata_way1[ 3],rdata_way1[ 2]} :
bank_sel_r[ 4] ? {rdata_way1[ 5],rdata_way1[ 4]} :
bank_sel_r[ 6] ? {rdata_way1[ 7],rdata_way1[ 6]} :
bank_sel_r[ 8] ? {rdata_way1[ 9],rdata_way1[ 8]} :
bank_sel_r[10] ? {rdata_way1[11],rdata_way1[10]} :
bank_sel_r[12] ? {rdata_way1[13],rdata_way1[12]} :
bank_sel_r[14] ? {rdata_way1[15],rdata_way1[14]} : 64'b0;
assign sram_rdata = hit_r[0] ? sram_rdata_way0 :
hit_r[1] ? sram_rdata_way1 : 64'b0;
wire [CACHELINE_WD -1:0] cacheline_old_way0, cacheline_old_way1;
assign cacheline_old_way0 = {
rdata_way0[15],
rdata_way0[14],
rdata_way0[13],
rdata_way0[12],
rdata_way0[11],
rdata_way0[10],
rdata_way0[ 9],
rdata_way0[ 8],
rdata_way0[ 7],
rdata_way0[ 6],
rdata_way0[ 5],
rdata_way0[ 4],
rdata_way0[ 3],
rdata_way0[ 2],
rdata_way0[ 1],
rdata_way0[ 0]
};
assign cacheline_old_way1 = {
rdata_way1[15],
rdata_way1[14],
rdata_way1[13],
rdata_way1[12],
rdata_way1[11],
rdata_way1[10],
rdata_way1[ 9],
rdata_way1[ 8],
rdata_way1[ 7],
rdata_way1[ 6],
rdata_way1[ 5],
rdata_way1[ 4],
rdata_way1[ 3],
rdata_way1[ 2],
rdata_way1[ 1],
rdata_way1[ 0]
};
assign cacheline_old = lru_r ? cacheline_old_way1 : cacheline_old_way0;
endmodule

18
lacpu/rtl/mycpu/csr.v
View File

@@ -63,9 +63,6 @@ module csr(
reg timer_en;
reg [63:0] timer_64;
// reg has_int_r;
// reg [ 1:0] plv_r;
wire inst_sc_w;
wire inst_csrrd;
wire inst_csrwr;
@@ -92,21 +89,6 @@ module csr(
wire va_error;
wire [31:0] bad_va;
// always @(posedge clk) begin
// if(reset) begin
// has_int_r <= 0;
// plv_r <= 0;
// end
// else begin
// has_int_r <= ((ecfg[`LIE] & estat[`IS]) != 13'b0) & crmd[`IE];
// plv_r <= except_en & !inst_ertn ? 2'b0 :
// inst_ertn ? prmd[`PPLV] :
// csr_we && (csr_addr == `CRMD_ADDR) ? csr_wdata[`PLV] :
// crmd[`PLV];
// end
// end
// out TODO!
assign has_int_out = ((ecfg[`LIE] & estat[`IS]) != 13'b0) & crmd[`IE];
assign plv_out = except_en & !inst_ertn ? 2'b0 :
inst_ertn ? prmd[`PPLV] :

12
lacpu/rtl/mycpu/dcache.v
View File

@@ -33,10 +33,10 @@ module dcache
.reset (reset ),
.flush (1'b0 ),
.stallreq (stallreq_dcache ),
.cached (~dcache_uncached ), // ? TODO from tlb
.sram_en (data_sram_en/* & ~d_refill & ~d_invalid & ~d_modify*/), // TODO!
.cached (~dcache_uncached ),
.sram_en (data_sram_en ),
.sram_we (data_sram_we ),
.sram_addr (data_sram_addr ), // _mmu ?
.sram_addr (data_sram_addr ),
.refresh (dcache_refresh ),
.miss (dcache_miss ),
.axi_raddr (dcache_raddr ),
@@ -52,10 +52,10 @@ module dcache
.write_back (dcache_write_back ),
.hit (dcache_hit ),
.lru (dcache_lru ),
.cached (~dcache_uncached ), // ? from tlb
.sram_en (data_sram_en/* & ~d_refill & ~d_invalid & ~d_modify*/), // TODO!
.cached (~dcache_uncached ),
.sram_en (data_sram_en ),
.sram_we (data_sram_we ),
.sram_addr (data_sram_addr ), // _mmu ?
.sram_addr (data_sram_addr ),
.sram_wdata (data_sram_wdata ),
.sram_rdata (data_sram_rdata ),
.refresh (dcache_refresh ),

2
lacpu/rtl/mycpu/dt.v → lacpu/rtl/mycpu/dt_stage.v
View File

@@ -1,4 +1,4 @@
module dt
module dt_stage
#(
parameter ES_TO_DT_BUS_WD = 340,
parameter DT_TO_MS_BUS_WD = 271,

46
lacpu/rtl/mycpu/exe_stage.v
View File

@@ -13,7 +13,6 @@ module exe_stage
input [ 5:0] stall,
output stallreq_es,
//output stallreq_es_for_cache,
input [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus,
output [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus,
@@ -22,18 +21,9 @@ module exe_stage
input src2_is_forward,
input [31:0] src1_forward_result,
input [31:0] src2_forward_result,
//input [MS_TO_ES_BUS_WD -1:0] dts_to_es_bus,
//input [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus,
//input [MS_TO_ES_BUS_WD -1:0] ms2_to_es_bus,
//input [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus,
output [BR_BUS_WD -1:0] br_bus,
input br_taken_buffer
// output data_sram_en,
// output [ 3:0] data_sram_we,
// output [31:0] data_sram_addr,
// output [31:0] data_sram_wdata
);
reg [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus_r;
@@ -130,26 +120,6 @@ module exe_stage
inst //31 :0
} = ds_to_es_bus_r;
// assign {dts_reg_we,
// dts_dest,
// dts_result
// } = dts_to_es_bus;
// assign {ms1_reg_we,
// ms1_dest,
// ms1_result
// } = ms1_to_es_bus;
// assign {ms2_reg_we,
// ms2_dest,
// ms2_result
// } = ms2_to_es_bus;
// assign {ws_reg_we,
// ws_dest,
// ws_result
// } = ws_to_es_bus;
assign es_to_dts_bus = {data_sram_en ,//339:339
data_sram_we ,//338:335
data_sram_addr ,//334:303
@@ -191,18 +161,10 @@ module exe_stage
end
end
assign src1 = //dts_reg_we & (dts_dest == rj ) & (rj != 1'b0) ? dts_result : // TODO!
//ms1_reg_we & (ms1_dest == rj ) & (rj != 1'b0) ? ms1_result : // TODO!
//ms2_reg_we & (ms2_dest == rj ) & (rj != 1'b0) ? ms2_result :
//ws_reg_we & (ws_dest == rj ) & (rj != 1'b0) ? ws_result :
src1_is_forward ? src1_forward_result :
rj_value;
assign src2 = //dts_reg_we & (dts_dest == rkd) & (rkd != 1'b0) ? dts_result : // TODO!
//ms1_reg_we & (ms1_dest == rkd) & (rkd != 1'b0) ? ms1_result : // TODO!
//ms2_reg_we & (ms2_dest == rkd) & (rkd != 1'b0) ? ms2_result :
//ws_reg_we & (ws_dest == rkd) & (rkd != 1'b0) ? ws_result :
src2_is_forward ? src2_forward_result :
rkd_value;
assign src1 = src1_is_forward ? src1_forward_result :
rj_value;
assign src2 = src2_is_forward ? src2_forward_result :
rkd_value;
assign alu_src1 = src1_is_pc ? es_pc :
src1;

6
lacpu/rtl/mycpu/icache.v
View File

@@ -31,9 +31,9 @@ module icache
.flush (1'b0 ),
.stallreq (stallreq_icache ),
.cached (1'b1 ),
.sram_en (inst_sram_en/* & ~i_refill & ~i_invalid*/ ), // TODO!
.sram_en (inst_sram_en ),
.sram_we (inst_sram_we ),
.sram_addr (inst_sram_addr ), // _mmu ?
.sram_addr (inst_sram_addr ),
.refresh (icache_refresh ),
.miss (icache_miss ),
.axi_raddr (icache_raddr ),
@@ -50,7 +50,7 @@ module icache
.hit (icache_hit ),
.lru (icache_lru ),
.cached (1'b1 ),
.sram_en (inst_sram_en/* & ~i_refill & ~i_invalid*/ ), // TODO!
.sram_en (inst_sram_en ),
.sram_we (inst_sram_we ),
.sram_addr (inst_sram_addr ),
.sram_wdata (inst_sram_wdata ),

43
lacpu/rtl/mycpu/id_stage.v
View File

@@ -30,9 +30,6 @@ module id_stage
reg [31:0] inst_sram_rdata_r;
reg stall_flag;
reg [ 6:0] es_load_buffer;
reg es_csr_buffer;
wire br_flush;
wire [31:0] ds_pc;
@@ -75,13 +72,6 @@ module id_stage
wire [31:0] rj_value;
wire [31:0] rkd_value;
wire [ 4:0] es_dest;
wire es_is_load;
wire es_is_csr;
wire es_reg_we;
wire stallreq_load;
wire stallreq_csr;
wire excp_adef;
wire [31:0] csr_vec_l;
wire [63:0] csr_vec;
@@ -219,37 +209,4 @@ module id_stage
assign rj_value = rf_rdata1;
assign rkd_value = rf_rdata2;
always @ (posedge clk) begin
if (reset) begin
es_load_buffer <= 7'b0;
es_csr_buffer <= 1'b0;
end
else if (flush) begin
es_load_buffer <= 7'b0;
es_csr_buffer <= 1'b0;
end
else if (stall[2]&(!stall[3])) begin
es_load_buffer <= 7'b0;
es_csr_buffer <= 1'b0;
end
else if (!stall[2]) begin
es_load_buffer <= {|load_op, reg_we, dest};
es_csr_buffer <= |csr_op;
end
end
assign {es_is_load,
es_reg_we,
es_dest
} = es_load_buffer;
assign es_is_csr = es_csr_buffer;
//ex段为load指令，且发生数据相关时，id段需要被暂停
assign stallreq_load = es_is_load & es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0)); //TODO?
assign stallreq_csr = es_is_csr & es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0));
wire stallreq_forward;
assign stallreq_forward = es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0)); // TODO!
assign stallreq_ds = stallreq_load | stallreq_csr/* | stallreq_forward*/;
endmodule

8
lacpu/rtl/mycpu/inst_decoder.v
View File

@@ -34,8 +34,6 @@ module inst_decoder(
output csr_wdata_sel,
output [31:0] csr_vec_l,
//output [ 3:0] sel_rf_res,
output reg_we
);
wire dest_is_r1;
@@ -536,10 +534,4 @@ module inst_decoder(
//inst_idle ;
assign excp_ipe = kernel_inst && (csr_plv == 2'b11);
// rf_res from
// assign sel_rf_res[0] = inst_jirl | inst_bl;
// assign sel_rf_res[1] = |load_op;
// assign sel_rf_res[2] = |csr_op;
// assign sel_rf_res[3] = |mul_div_op;
endmodule

2
lacpu/rtl/mycpu/mem_stage.v
View File

@@ -214,7 +214,7 @@ module mem2_stage
(inst_ld_hu & byte_sel[0]) ? { 16'b0, data_temp[15: 0]} :
(inst_ld_hu & byte_sel[2]) ? { 16'b0, data_temp[31:16]} :
(inst_ld_w & byte_sel[0]) ? data_temp :
32'b0; // inst_ll ?
32'b0;
assign {csr_we,
csr_wdata_sel,

10
lacpu/rtl/mycpu/mul.v
View File

@@ -16,6 +16,7 @@ module mul(
wire carry;
wire [63:0] mul_result;
reg [63:0] mul_result_r;
always @ (posedge clk) begin
if (reset) begin
@@ -25,7 +26,7 @@ module mul(
cnt <= cnt - 1;
end
else if (in_valid) begin
cnt <= 1;//32;
cnt <= 2;//32;
end
end
@@ -35,15 +36,18 @@ module mul(
if (reset) begin
result_h <= 0;
result_l <= 0;
mul_result_r <= 0;
end
else if (cnt != 0) begin
//{result_h, result_l} <= {carry, add_result, result_l[31:1]};
result_h <= mul_result[63:32];
result_l <= mul_result[31: 0];
result_h <= mul_result_r[63:32];
result_l <= mul_result_r[31: 0];
mul_result_r <= mul_result;
end
else if (in_valid) begin
result_h <= 0;
result_l <= 0;//b;
mul_result_r <= 0;
end
end

10
lacpu/rtl/mycpu/mul_div_top.v
View File

@@ -32,16 +32,6 @@ module mul_div_top(
wire sign_flag_locked;
wire rem_flag_locked;
//-------------------------
wire [63:0] unsigned_prod;
wire [63:0] signed_prod;
assign unsigned_prod = a * b;
//assign signed_prod = $signed(a) * $signed(b);
//-------------------------
assign mul_en = mul_div_op[0] | mul_div_op[1];
assign div_en = mul_div_op[2] | mul_div_op[3];

2
lacpu/rtl/mycpu/mycpu_core.v
View File

@@ -173,7 +173,7 @@ module mycpu_core
.br_taken_buffer (br_taken_buffer )
);
dt dt(
dt_stage dt_stage(
.clk (clk ),
.reset (reset ),
.flush (flush ),

25
lacpu/rtl/mycpu/mycpu_top.v
View File

@@ -52,18 +52,6 @@ module mycpu_top
input bvalid,
output bready,
// // inst sram interface
// output inst_sram_en,
// output [ 3:0] inst_sram_we,
// output [31:0] inst_sram_addr,
// output [31:0] inst_sram_wdata,
// input [31:0] inst_sram_rdata,
// // data sram interface
// output data_sram_en,
// output [ 3:0] data_sram_we,
// output [31:0] data_sram_addr,
// output [31:0] data_sram_wdata,
// input [31:0] data_sram_rdata,
// trace debug interface
output [31:0] debug_wb_pc,
output [ 3:0] debug_wb_rf_we,
@@ -223,25 +211,12 @@ module mycpu_top
end
assign data_sram_rdata = dcache_cached_r ? dcache_temp_rdata : uncache_temp_rdata;
// mmu u_inst_mmu(
// .addr_i (inst_sram_addr ),
// .addr_o (inst_sram_addr_mmu ),
// .cache_v (icache_cached )
// );
mmu data_mmu(
.addr_i (data_sram_addr ),
.addr_o (data_sram_addr_mmu ),
.cache_v (dcache_cached )
);
// cache signal from tlb
// begin
//assign dcache_uncached = 1'b0;
// end
axi_ctrl_v5 axi_ctrl(
.clk (clk ),
.reset (~resetn ),

15
lacpu/rtl/mycpu/pip_ctrl.v
View File

@@ -34,24 +34,11 @@ module pip_ctrl(
flush = 0;
stall = `StallBus'b111111;
end
//id段å<C2B5>‘生暂å<E2809A>œï¼Œæ­¤æ—¶idå<64>Šä¹‹å‰<C3A5>æš‚å<E2809A>?
else if (stallreq_ds) begin
flush = 0;
stall = `StallBus'b000111;
end
// else if(stallreq_fs_for_cache) begin
// flush = 0;
// stall = `StallBus'b000011;
// end
// else if(stallreq_es_for_cache) begin
// flush = 0;
// stall = `StallBus'b011111;
// end
// else if(stallreq_cache) begin
// flush = 0;
// stall = `StallBus'b111111;
// end
else begin
flush = 0;
stall = `StallBus'b000000;

7
lacpu/rtl/mycpu/uncache.v
View File

@@ -50,13 +50,6 @@ module uncache
end
end
// assign rd_req = conf_en & ~valid & ~(|conf_we);
// assign rd_addr = conf_addr;
// assign wr_req = conf_en & ~valid & (|conf_we);
// assign wr_wstrb = conf_we;
// assign wr_addr = conf_addr;
// assign wr_data = conf_wdata;
always @ (posedge clk) begin
if (!resetn) begin
conf_rdata <= 32'b0;