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[Modified] finish loaduse & fix little bug

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包焕垲
2023-05-29 11:53:25 +08:00
parent 144623175a
commit f660bd337b
6 changed files with 84 additions and 66 deletions
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32
lacpu/rtl/cpu/loaduse.v
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@@ -1,39 +1,19 @@
`include "mycpu.v"
module loaduse(
input clk,
input reset,
module loaduse(
input [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus,
input [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus,
output loaduse
output lu_to_es_bus
);
wire [4:0] ds_rf_raddr1;
wire [4:0] ds_rf_raddr2;
wire [4:0] es_load_op;
wire [4:0] es_dest;
reg [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus_reg;
reg [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus_reg;
wire loaduse;
assign {ds_rf_raddr1, ds_rf_raddr2} = ds_to_lu_bus;
assign {es_dest , es_load_op } = es_to_lu_bus;
always @(posedge clk) begin
if(reset) begin
ds_to_lu_bus_reg <= 0;
es_to_lu_bus_reg <= 0;
end
else begin
ds_to_lu_bus_reg <= ds_to_lu_bus;
es_to_lu_bus_reg <= es_to_lu_bus;
end
end
assign {ds_rf_rdata1, ds_rf_rdata2} = ds_to_lu_bus_reg;
assign {es_dest , es_load_op } = es_to_lu_bus_reg;
assign loaduse = ^es_load_op &&
(((ds_rf_rdata1 == es_dest) && (ds_rf_rdata1 != 5'b0)) || ((ds_rf_rdata2 == es_dest) && (ds_rf_rdata2 != 5'b0)));
assign lu_to_es_bus = ^es_load_op &&
(((ds_rf_raddr1 == es_dest) && (ds_rf_raddr1 != 5'b0)) || ((ds_rf_raddr2 == es_dest) && (ds_rf_raddr2 != 5'b0)));
endmodule