From f660bd337b21474cf6eec5bba3b8523d2707fa29 Mon Sep 17 00:00:00 2001 From: UnbalancedCat Date: Mon, 29 May 2023 11:53:25 +0800 Subject: [PATCH] [Modified] finish loaduse & fix little bug --- lacpu/rtl/cpu/cpu_top.v | 20 +++++++-- lacpu/rtl/cpu/exe_stage.v | 73 ++++++++++++++++++++------------ lacpu/rtl/cpu/id_stage.v | 8 +++- lacpu/rtl/cpu/loaduse.v | 32 +++----------- lacpu/rtl/cpu/mem_stage.v | 2 +- lacpu/run_vivado/la32r/la32r.xpr | 15 +++---- 6 files changed, 84 insertions(+), 66 deletions(-) diff --git a/lacpu/rtl/cpu/cpu_top.v b/lacpu/rtl/cpu/cpu_top.v index 8a95379..8fa5906 100755 --- a/lacpu/rtl/cpu/cpu_top.v +++ b/lacpu/rtl/cpu/cpu_top.v @@ -62,6 +62,9 @@ module mycpu_top( wire [`FW_TO_ES_BUS_WD -1:0] fw_to_es_bus; wire [`MS_TO_ES_BUS_WD -1:0] ms_to_es_bus; wire [`WS_TO_ES_BUS_WD -1:0] ws_to_es_bus; + wire [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus; + wire [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus; + wire lu_to_es_bus; // IF stage @@ -97,8 +100,10 @@ module mycpu_top( .ds_to_es_bus (ds_to_es_bus ), //to rf: for write back .ws_to_rf_bus (ws_to_rf_bus ), - - .ds_to_fw_bus (ds_to_fw_bus ) + //to fw + .ds_to_fw_bus (ds_to_fw_bus ), + //to lu + .ds_to_lu_bus (ds_to_lu_bus ) ); // EXE stage exe_stage exe_stage( @@ -121,6 +126,10 @@ module mycpu_top( .ms_to_ds_bus (ms_to_es_bus ), //from ws .ws_to_ds_bus (ws_to_es_bus ), + //to lu + .es_to_lu_bus (es_to_lu_bus ), + //from lu + .lu_to_es_bus (lu_to_es_bus ), // data sram interface .data_sram_en (data_sram_en ), .data_sram_wen (data_sram_wen ), @@ -194,8 +203,13 @@ module mycpu_top( .ds_to_fw_bus (ds_to_fw_bus), .es_to_fw_bus (es_to_fw_bus), .ms_to_fw_bus (ms_to_fw_bus), - .fw_to_es_bus (fw_to_es_bus) ); + //Loaduse + loaduse loaduse( + .ds_to_lu_bus (ds_to_lu_bus), + .es_to_lu_bus (es_to_lu_bus), + .lu_to_es_bus (lu_to_es_bus) + ); endmodule diff --git a/lacpu/rtl/cpu/exe_stage.v b/lacpu/rtl/cpu/exe_stage.v index 2669e7f..0367a94 100755 --- a/lacpu/rtl/cpu/exe_stage.v +++ b/lacpu/rtl/cpu/exe_stage.v @@ -25,6 +25,10 @@ module exe_stage( input [`MS_TO_ES_BUS_WD -1:0] ms_to_ds_bus , //from ws input [`WS_TO_ES_BUS_WD -1:0] ws_to_ds_bus , + //to lu + output [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus , + //from lu + input lu_to_es_bus , //div output [31:0] div_divisor_data , output div_divisor_valid , @@ -74,6 +78,9 @@ module exe_stage( wire es_src2_is_ms_dest; wire es_data_is_rf_wdata; + wire lu_to_es_bus_r; + reg loaduse_r; + assign {es_alu_op , //173:155 es_src1_is_pc , //154:154 es_src2_is_imm , //153:153 @@ -99,7 +106,7 @@ module exe_stage( } = fw_to_es_bus; assign ms_alu_result = ms_to_ds_bus; - assign ws_rf_wdata = ws_to_ds_bus; + assign ws_rf_wdata = ws_to_ds_bus; wire [31:0] br_target; @@ -112,13 +119,13 @@ module exe_stage( wire es_Zero ; wire [31:0] es_result ; - reg div_divisor_valid_reg; + reg div_divisor_valid_r; reg div_divisor_ready_flag; - reg div_dividend_valid_reg; + reg div_dividend_valid_r; reg div_dividend_ready_flag; - reg divu_divisor_valid_reg; + reg divu_divisor_valid_r; reg divu_divisor_ready_flag; - reg divu_dividend_valid_reg; + reg divu_dividend_valid_r; reg divu_dividend_ready_flag; wire es_inst_divw ; @@ -151,7 +158,9 @@ module exe_stage( es_mem_we }; - assign es_ready_go = (is_div_mod && !(div_dout_valid || divu_dout_valid)) ? 1'b1 : 1'b0; + assign es_to_lu_bus = {es_dest, es_load_op}; + + assign es_ready_go = (is_div_mod && !(div_dout_valid || divu_dout_valid)) || loaduse_r ? 1'b1 : 1'b0; assign es_allowin = !es_valid || es_ready_go && ms_allowin; assign es_to_ms_valid = es_valid && es_ready_go; always @(posedge clk) begin @@ -167,6 +176,18 @@ module exe_stage( end end + always @(posedge clk) begin + if(reset) begin + loaduse_r <= 1'b0; + end + else if(loaduse_r == 1'b1) begin + loaduse_r <= 1'b0; + end + else begin + loaduse_r <= lu_to_es_bus; + end + end + assign es_alu_src1 = es_src1_is_pc ? es_pc : es_src1_is_es_dest ? ms_alu_result : es_src1_is_ms_dest ? ws_rf_wdata : @@ -190,15 +211,15 @@ module exe_stage( always @(posedge clk) begin if(reset) begin - div_divisor_valid_reg <= 1'b0; + div_divisor_valid_r <= 1'b0; div_divisor_ready_flag <= 1'b0; end - else if(div_divisor_valid_reg && div_divisor_ready) begin - div_divisor_valid_reg <= 1'b0; + else if(div_divisor_valid_r && div_divisor_ready) begin + div_divisor_valid_r <= 1'b0; div_divisor_ready_flag <= 1'b1; end else if((es_inst_divw || es_inst_modw) && !div_divisor_ready_flag) begin - div_divisor_valid_reg <= 1'b1; + div_divisor_valid_r <= 1'b1; end else if(es_ready_go) begin div_divisor_ready_flag <= 1'b0; @@ -206,15 +227,15 @@ module exe_stage( end always @(posedge clk) begin if(reset) begin - div_dividend_valid_reg <= 1'b0; + div_dividend_valid_r <= 1'b0; div_dividend_ready_flag <= 1'b0; end - else if(div_dividend_valid_reg && div_dividend_ready) begin - div_dividend_valid_reg <= 1'b0; + else if(div_dividend_valid_r && div_dividend_ready) begin + div_dividend_valid_r <= 1'b0; div_dividend_ready_flag <= 1'b1; end else if((es_inst_divw || es_inst_modw) && !div_dividend_ready_flag) begin - div_dividend_valid_reg <= 1'b1; + div_dividend_valid_r <= 1'b1; end else if(es_ready_go) begin div_dividend_ready_flag <= 1'b0; @@ -222,15 +243,15 @@ module exe_stage( end always @(posedge clk) begin if(reset) begin - divu_divisor_valid_reg <= 1'b0; + divu_divisor_valid_r <= 1'b0; divu_divisor_ready_flag <= 1'b0; end - else if(divu_divisor_valid_reg && divu_divisor_ready) begin - divu_divisor_valid_reg <= 1'b0; + else if(divu_divisor_valid_r && divu_divisor_ready) begin + divu_divisor_valid_r <= 1'b0; divu_divisor_ready_flag <= 1'b1; end else if((es_inst_divw || es_inst_modw) && !divu_divisor_ready_flag) begin - divu_divisor_valid_reg <= 1'b1; + divu_divisor_valid_r <= 1'b1; end else if(es_ready_go) begin divu_divisor_ready_flag <= 1'b0; @@ -238,25 +259,25 @@ module exe_stage( end always @(posedge clk) begin if(reset) begin - divu_dividend_valid_reg <= 1'b0; + divu_dividend_valid_r <= 1'b0; divu_dividend_ready_flag <= 1'b0; end - else if(divu_dividend_valid_reg && divu_dividend_ready) begin - divu_dividend_valid_reg <= 1'b0; + else if(divu_dividend_valid_r && divu_dividend_ready) begin + divu_dividend_valid_r <= 1'b0; divu_dividend_ready_flag <= 1'b1; end else if((es_inst_divw || es_inst_modw) && !divu_dividend_ready_flag) begin - divu_dividend_valid_reg <= 1'b1; + divu_dividend_valid_r <= 1'b1; end else if(es_ready_go) begin divu_dividend_ready_flag <= 1'b0; end end - assign div_divisor_valid = div_divisor_valid_reg; - assign div_dividend_valid = div_dividend_valid_reg; - assign divu_divisor_valid = divu_divisor_valid_reg; - assign divu_dividend_valid = divu_dividend_valid_reg; + assign div_divisor_valid = div_divisor_valid_r; + assign div_dividend_valid = div_dividend_valid_r; + assign divu_divisor_valid = divu_divisor_valid_r; + assign divu_dividend_valid = divu_dividend_valid_r; assign div_mod_result = es_inst_divw ? div_dout_data[63:32] : es_inst_modw ? div_dout_data[31: 0] : diff --git a/lacpu/rtl/cpu/id_stage.v b/lacpu/rtl/cpu/id_stage.v index 67ce21e..9dfa501 100755 --- a/lacpu/rtl/cpu/id_stage.v +++ b/lacpu/rtl/cpu/id_stage.v @@ -16,7 +16,9 @@ module id_stage( //to fs input [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus , //to fw - output [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus + output [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus , + //to lu + output [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus ); @@ -142,6 +144,8 @@ module id_stage( assign ds_to_fw_bus = {rf_raddr1 , rf_raddr2}; + assign ds_to_lu_bus = {rf_raddr1 , rf_raddr2}; + assign ds_ready_go = 1'b1; assign ds_allowin = !ds_valid || ds_ready_go && es_allowin; assign ds_to_es_valid = ds_valid && ds_ready_go; @@ -246,7 +250,7 @@ module id_stage( assign src1_is_pc = inst_bl | inst_jirl | inst_pcaddu12i; assign src2_is_4 = inst_bl | inst_jirl; - assign src2_is_imm = inst_addiw | inst_lu12iw | inst_pcaddu12i | inst_andi | inst_ori | inst_xori | inst_slliw | inst_srliw | inst_sraiw | inst_ldb | inst_ldh | inst_ldw | inst_ldbu | inst_ldhu | inst_stb | inst_sth | inst_stw; + assign src2_is_imm = inst_addiw | inst_lu12iw | inst_pcaddu12i | inst_andi | inst_ori | inst_xori | inst_slliw | inst_srliw | inst_sraiw | inst_ldb | inst_ldh | inst_ldw | inst_ldbu | inst_ldhu | inst_stb | inst_sth | inst_stw | inst_mulhwu | inst_divwu | inst_modwu; assign dst_is_r1 = inst_bl; assign reg_we = ~(inst_beq | inst_bne | inst_bge | inst_bgeu | inst_blt | inst_bltu | inst_b | inst_stw | inst_sth | inst_stb); diff --git a/lacpu/rtl/cpu/loaduse.v b/lacpu/rtl/cpu/loaduse.v index 9218223..164e832 100644 --- a/lacpu/rtl/cpu/loaduse.v +++ b/lacpu/rtl/cpu/loaduse.v @@ -1,39 +1,19 @@ `include "mycpu.v" -module loaduse( - input clk, - input reset, - +module loaduse( input [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus, input [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus, - output loaduse + output lu_to_es_bus ); wire [4:0] ds_rf_raddr1; wire [4:0] ds_rf_raddr2; wire [4:0] es_load_op; wire [4:0] es_dest; - - reg [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus_reg; - reg [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus_reg; - wire loaduse; + assign {ds_rf_raddr1, ds_rf_raddr2} = ds_to_lu_bus; + assign {es_dest , es_load_op } = es_to_lu_bus; - always @(posedge clk) begin - if(reset) begin - ds_to_lu_bus_reg <= 0; - es_to_lu_bus_reg <= 0; - end - else begin - ds_to_lu_bus_reg <= ds_to_lu_bus; - es_to_lu_bus_reg <= es_to_lu_bus; - end - end - - - assign {ds_rf_rdata1, ds_rf_rdata2} = ds_to_lu_bus_reg; - assign {es_dest , es_load_op } = es_to_lu_bus_reg; - - assign loaduse = ^es_load_op && - (((ds_rf_rdata1 == es_dest) && (ds_rf_rdata1 != 5'b0)) || ((ds_rf_rdata2 == es_dest) && (ds_rf_rdata2 != 5'b0))); + assign lu_to_es_bus = ^es_load_op && + (((ds_rf_raddr1 == es_dest) && (ds_rf_raddr1 != 5'b0)) || ((ds_rf_raddr2 == es_dest) && (ds_rf_raddr2 != 5'b0))); endmodule \ No newline at end of file diff --git a/lacpu/rtl/cpu/mem_stage.v b/lacpu/rtl/cpu/mem_stage.v index 03ff65d..4989ddf 100755 --- a/lacpu/rtl/cpu/mem_stage.v +++ b/lacpu/rtl/cpu/mem_stage.v @@ -83,7 +83,7 @@ module mem_stage( end if (es_to_ms_valid && ms_allowin) begin - es_to_ms_bus_r = es_to_ms_bus; + es_to_ms_bus_r <= es_to_ms_bus; end end diff --git a/lacpu/run_vivado/la32r/la32r.xpr b/lacpu/run_vivado/la32r/la32r.xpr index bb50bde..3afa387 100644 --- a/lacpu/run_vivado/la32r/la32r.xpr +++ b/lacpu/run_vivado/la32r/la32r.xpr @@ -117,6 +117,13 @@ + + + + + + + @@ -152,14 +159,6 @@ - - - - - - - -