19 lines
604 B
Verilog
19 lines
604 B
Verilog
`include "mycpu.v"
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module loaduse(
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input [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus,
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input [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus,
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output lu_to_es_bus
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);
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wire [4:0] ds_rf_raddr1;
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wire [4:0] ds_rf_raddr2;
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wire [4:0] es_load_op;
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wire [4:0] es_dest;
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assign {ds_rf_raddr1, ds_rf_raddr2} = ds_to_lu_bus;
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assign {es_dest , es_load_op } = es_to_lu_bus;
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assign lu_to_es_bus = ^es_load_op &&
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(((ds_rf_raddr1 == es_dest) && (ds_rf_raddr1 != 5'b0)) || ((ds_rf_raddr2 == es_dest) && (ds_rf_raddr2 != 5'b0)));
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endmodule |