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[Modified] Fix bugs & 29 Functional Test Point PASS

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This commit is contained in:
包焕垲
2023-06-26 15:11:31 +08:00
parent 75644e4920
commit 78fe1f6cf5
12 changed files with 91 additions and 86 deletions
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5
lacpu/rtl/cpu/alu.v
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@@ -44,9 +44,6 @@ module alu(
wire [31:0] sll_result; wire [31:0] sll_result;
wire [63:0] sr64_result; wire [63:0] sr64_result;
wire [31:0] sr_result; wire [31:0] sr_result;
wire [63:0] mul64_result;
wire [63:0] mulu64_result;
wire [31:0] mul_result;
// 32-bit adder // 32-bit adder
wire [31:0] adder_a; wire [31:0] adder_a;
@@ -77,7 +74,7 @@ module alu(
assign or_result = alu_src1 | alu_src2; assign or_result = alu_src1 | alu_src2;
assign nor_result = ~or_result; assign nor_result = ~or_result;
assign xor_result = alu_src1 ^ alu_src2; assign xor_result = alu_src1 ^ alu_src2;
assign lui_result = {alu_src2[19:0], 12'b0}; assign lui_result = alu_src2;
// SLL result // SLL result
assign sll_result = alu_src1 << alu_src2[4:0]; assign sll_result = alu_src1 << alu_src2[4:0];

52
lacpu/rtl/cpu/exe_stage.v
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@@ -1,7 +1,7 @@
module exe_stage module exe_stage
#( #(
parameter BR_BUS_WD = 33, parameter BR_BUS_WD = 33,
parameter DS_TO_ES_BUS_WD = 206, parameter DS_TO_ES_BUS_WD = 237,
parameter ES_TO_MS_BUS_WD = 175, parameter ES_TO_MS_BUS_WD = 175,
parameter MS_TO_ES_BUS_WD = 38, parameter MS_TO_ES_BUS_WD = 38,
parameter WS_TO_ES_BUS_WD = 38 parameter WS_TO_ES_BUS_WD = 38
@@ -22,7 +22,7 @@ module exe_stage
output [BR_BUS_WD -1:0] br_bus, output [BR_BUS_WD -1:0] br_bus,
output data_sram_en, output data_sram_en,
output [ 7:0] data_sram_we, output [ 3:0] data_sram_we,
output [31:0] data_sram_addr, output [31:0] data_sram_addr,
output [31:0] data_sram_wdata output [31:0] data_sram_wdata
); );
@@ -71,32 +71,32 @@ module exe_stage
wire data_sram_en_temp; wire data_sram_en_temp;
wire stallreq_for_mul_div; wire stallreq_for_mul_div;
wire [31:0] mul_div_result; wire [31:0] mul_div_result; // TODO!!!
wire [31:0] es_result; wire [31:0] es_result;
wire [31:0] csr_wdata; wire [31:0] csr_wdata;
wire [63:0] csr_bus; wire [63:0] csr_bus;
assign {csr_op ,//205:199 assign {csr_op ,//236:230
csr_wdata_sel ,//198:198 csr_wdata_sel ,//229:229
csr_addr ,//197:184 csr_addr ,//228:215
csr_we ,//183:183 csr_we ,//214:214
alu_op ,//182:171 alu_op ,//213:202
mul_div_op ,//170:167 mul_div_op ,//198:189
mul_div_sign ,//166:166 mul_div_sign ,//197:197
branch_op ,//165:157 branch_op ,//196:188
store_op ,//156:154 store_op ,//187:185
load_op ,//153:148 load_op ,//184:179
reg_we ,//147:147 reg_we ,//178:178
src1_is_pc ,//146:146 src1_is_pc ,//177:177
src2_is_imm ,//145:145 src2_is_imm ,//176:176
src2_is_4 ,//144:144 src2_is_4 ,//175:175
rj ,//143:139 rj ,//174:170
rkd ,//138:134 rkd ,//169:165
rj_value ,//133:102 rj_value ,//164:133
rkd_value ,//101:70 rkd_value ,//132:101
dest ,//69 :65 dest ,//100:96
imm ,//95 :64 imm ,//95 :64
es_pc ,//63 :32 es_pc ,//63 :32
inst //31 :0 inst //31 :0
@@ -176,8 +176,8 @@ module exe_stage
wire csr_cancel; wire csr_cancel;
wire csr_cancel_reg; wire csr_cancel_reg;
assign csr_cancel = 1'b1; assign csr_cancel = 1'b0;
assign csr_cancel_reg = 1'b1; //TODO! assign csr_cancel_reg = 1'b0; //TODO!
assign br_bus = {br_taken & ~(csr_cancel|csr_cancel_reg), assign br_bus = {br_taken & ~(csr_cancel|csr_cancel_reg),
br_target br_target
@@ -186,8 +186,8 @@ module exe_stage
lsu u_lsu( lsu u_lsu(
.load_op (load_op ), .load_op (load_op ),
.store_op (store_op ), .store_op (store_op ),
.rj_value (rj_value ), .rj_value (src1 ),
.rkd_value (rkd_value ), .rkd_value (src2 ),
.imm (imm ), .imm (imm ),
.data_sram_en (data_sram_en_temp), .data_sram_en (data_sram_en_temp),

51
lacpu/rtl/cpu/id_stage.v
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@@ -1,7 +1,7 @@
module id_stage module id_stage
#( #(
parameter FS_TO_DS_BUS_WD = 32, parameter FS_TO_DS_BUS_WD = 32,
parameter DS_TO_ES_BUS_WD = 206, parameter DS_TO_ES_BUS_WD = 237,
parameter WS_TO_RF_BUS_WD = 38 parameter WS_TO_RF_BUS_WD = 38
) )
( (
@@ -12,7 +12,7 @@ module id_stage
input [ 5:0] stall, input [ 5:0] stall,
input br_taken, input br_taken,
output stallreq_id, output stallreq_ds,
input pc_valid, input pc_valid,
input [31:0] inst_sram_rdata, input [31:0] inst_sram_rdata,
@@ -62,12 +62,12 @@ module id_stage
wire [31:0] inst; wire [31:0] inst;
wire [31:0] next_inst; wire [31:0] next_inst;
wire rf_raddr1; wire [ 4:0] rf_raddr1;
wire [31:0] rf_rdata1; wire [31:0] rf_rdata1;
wire rf_raddr2; wire [ 4:0] rf_raddr2;
wire [31:0] rf_rdata2; wire [31:0] rf_rdata2;
wire rf_we; wire rf_we;
wire rf_waddr; wire [ 4:0] rf_waddr;
wire [31:0] rf_wdata; wire [31:0] rf_wdata;
wire [31:0] rj_value; wire [31:0] rj_value;
@@ -91,25 +91,25 @@ module id_stage
assign csr_vec_l = 0; //TODO! assign csr_vec_l = 0; //TODO!
assign csr_vec = {csr_vec_h_r, csr_vec_l}; assign csr_vec = {csr_vec_h_r, csr_vec_l};
assign ds_to_es_bus = {csr_op ,//205:199 assign ds_to_es_bus = {csr_op ,//236:230
csr_wdata_sel ,//198:198 csr_wdata_sel ,//229:229
csr_addr ,//197:184 csr_addr ,//228:215
csr_we ,//183:183 csr_we ,//214:214
alu_op ,//182:171 alu_op ,//213:202
mul_div_op & {4{pc_valid_r}} ,//170:167 mul_div_op & {4{pc_valid_r}} ,//198:189
mul_div_sign & pc_valid_r ,//166:166 mul_div_sign & pc_valid_r ,//197:197
branch_op & {9{pc_valid_r}} ,//165:157 branch_op & {9{pc_valid_r}} ,//196:188
store_op & {3{pc_valid_r}} ,//156:154 store_op & {3{pc_valid_r}} ,//187:185
load_op & {6{pc_valid_r}} ,//153:148 load_op & {6{pc_valid_r}} ,//184:179
reg_we & pc_valid_r ,//147:147 reg_we & pc_valid_r ,//178:178
src1_is_pc ,//146:146 src1_is_pc ,//177:177
src2_is_imm ,//145:145 src2_is_imm ,//176:176
src2_is_4 ,//144:144 src2_is_4 ,//175:175
rj ,//143:139 rj ,//174:170
rkd ,//138:134 rkd ,//169:165
rj_value ,//133:102 rj_value ,//164:133
rkd_value ,//101:70 rkd_value ,//132:101
dest ,//69 :65 dest ,//100:96
imm ,//95 :64 imm ,//95 :64
ds_pc ,//63 :32 ds_pc ,//63 :32
inst & {32{pc_valid_r}} //31 :0 inst & {32{pc_valid_r}} //31 :0
@@ -195,7 +195,6 @@ module id_stage
.csr_op (csr_op ), .csr_op (csr_op ),
.csr_addr (csr_addr ), .csr_addr (csr_addr ),
.csr_wdata_sel (csr_wdata_sel ), .csr_wdata_sel (csr_wdata_sel ),
.sel_rf_res (sel_rf_res ),
.reg_we (reg_we ) .reg_we (reg_we )
); );
@@ -246,7 +245,7 @@ module id_stage
//ex段为load指令，且发生数据相关时，id段需要被暂停 //ex段为load指令，且发生数据相关时，id段需要被暂停
assign stallreq_load = ex_is_load & ex_rf_we & ((ex_rf_waddr==rj_value & rj_value!=0)|(ex_rf_waddr==rkd_value & rkd_value!=0)); assign stallreq_load = ex_is_load & ex_rf_we & ((ex_rf_waddr==rj_value & rj_value!=0)|(ex_rf_waddr==rkd_value & rkd_value!=0));
assign stallreq_csr = ex_is_csr & ex_rf_we & ((ex_rf_waddr==rj_value & rj_value!=0)|(ex_rf_waddr==rkd_value & rkd_value!=0)); assign stallreq_csr = ex_is_csr & ex_rf_we & ((ex_rf_waddr==rj_value & rj_value!=0)|(ex_rf_waddr==rkd_value & rkd_value!=0));
assign stallreq_id = stallreq_load | stallreq_csr; assign stallreq_ds = stallreq_load | stallreq_csr;
endmodule endmodule

11
lacpu/rtl/cpu/inst_decoder.v
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@@ -1,4 +1,3 @@
`include "tools.v"
module inst_decoder( module inst_decoder(
input [31:0] inst, input [31:0] inst,
@@ -31,7 +30,7 @@ module inst_decoder(
output csr_wdata_sel, output csr_wdata_sel,
//output [31:0] csr_vec_l, //output [31:0] csr_vec_l,
output [ 3:0] sel_rf_res, //output [ 3:0] sel_rf_res,
output reg_we output reg_we
); );
@@ -439,8 +438,8 @@ module inst_decoder(
// rf_res from // rf_res from
assign sel_rf_res[0] = inst_jirl | inst_bl; // assign sel_rf_res[0] = inst_jirl | inst_bl;
assign sel_rf_res[1] = |load_op; // assign sel_rf_res[1] = |load_op;
assign sel_rf_res[2] = |csr_op; // assign sel_rf_res[2] = |csr_op;
assign sel_rf_res[3] = |mul_div_op; // assign sel_rf_res[3] = |mul_div_op;
endmodule endmodule

6
lacpu/rtl/cpu/lsu.v
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@@ -6,9 +6,9 @@ module lsu(
input [31:0] imm, input [31:0] imm,
output data_sram_en, output data_sram_en,
output data_sram_we, output [ 3:0] data_sram_we,
output data_sram_addr, output [31:0] data_sram_addr,
output data_sram_wdata output [31:0] data_sram_wdata
); );
wire inst_ll_w; wire inst_ll_w;
wire inst_ld_b; wire inst_ld_b;

2
lacpu/rtl/cpu/mem_stage.v
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@@ -68,7 +68,7 @@ module mem_stage
assign ms_to_es_bus = {reg_we, assign ms_to_es_bus = {reg_we,
dest, dest,
es_result (|load_op) ? ms_result : es_result
}; };
assign ms_to_ws_bus = {reg_we ,//101:101 assign ms_to_ws_bus = {reg_we ,//101:101

17
lacpu/rtl/cpu/mycpu.v → lacpu/rtl/cpu/mycpu_top.v
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@@ -1,14 +1,14 @@
module mycpu module mycpu_top
#( #(
parameter FS_TO_DS_BUS_WD = 32, parameter FS_TO_DS_BUS_WD = 32,
parameter DS_TO_ES_BUS_WD = 206, parameter DS_TO_ES_BUS_WD = 237,
parameter ES_TO_MS_BUS_WD = 175, parameter ES_TO_MS_BUS_WD = 175,
parameter MS_TO_WS_BUS_WD = 102, parameter MS_TO_WS_BUS_WD = 102,
parameter WS_TO_RF_BUS_WD = 38, parameter WS_TO_RF_BUS_WD = 38,
parameter MS_TO_ES_BUS_WD = 32, parameter MS_TO_ES_BUS_WD = 38,
parameter WS_TO_ES_BUS_WD = 32, parameter WS_TO_ES_BUS_WD = 38,
parameter BR_BUS_WD = 33 parameter BR_BUS_WD = 33
) )
( (
@@ -44,11 +44,14 @@ module mycpu
wire [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus; wire [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;
wire [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus; wire [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
wire [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
wire [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
wire [BR_BUS_WD -1:0] br_bus; wire [BR_BUS_WD -1:0] br_bus;
wire flush; wire flush;
wire stallreq_es; wire stallreq_es;
wire stallreq_id; wire stallreq_ds;
wire [ 5:0] stall; wire [ 5:0] stall;
wire except_en; wire except_en;
wire [31:0] new_pc; wire [31:0] new_pc;
@@ -76,7 +79,7 @@ module mycpu
.flush (flush ), .flush (flush ),
.stall (stall ), .stall (stall ),
.br_taken (br_bus[32] ), .br_taken (br_bus[32] ),
.stallreq_id (stallreq_id ), .stallreq_ds (stallreq_ds ),
.fs_to_ds_bus (fs_to_ds_bus ), .fs_to_ds_bus (fs_to_ds_bus ),
.pc_valid (inst_sram_en ), .pc_valid (inst_sram_en ),
.inst_sram_rdata (inst_sram_rdata ), .inst_sram_rdata (inst_sram_rdata ),

12
lacpu/rtl/cpu/regfile.v
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@@ -56,13 +56,13 @@ module regfile(
end end
//READ OUT 1 //READ OUT 1
assign rdata1 = (raddr1==5'b0 ) ? 32'b0 : assign rdata1 = (raddr1==5'b0 ) ? 32'b0 :
(raddr1==waddr) ? wdata : (raddr1==waddr) & we ? wdata :
rf[raddr1]; rf[raddr1];
//READ OUT 2 //READ OUT 2
assign rdata2 = (raddr2==5'b0 ) ? 32'b0 : assign rdata2 = (raddr2==5'b0 ) ? 32'b0 :
(raddr2==waddr) ? wdata : (raddr2==waddr) & we ? wdata :
rf[raddr2]; rf[raddr2];
endmodule endmodule

1
lacpu/rtl/cpu/tools.v
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@@ -1,3 +1,4 @@
`default_nettype wire
module decoder_2_4( module decoder_2_4(
input [ 1:0] in, input [ 1:0] in,
output [ 3:0] out output [ 3:0] out

2
lacpu/rtl/cpu/wb_stage.v
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@@ -62,7 +62,7 @@ module wb_stage
assign debug_wb_pc = ws_pc; assign debug_wb_pc = ws_pc;
assign debug_wb_rf_we = {4{reg_we}}; assign debug_wb_rf_we = {4{reg_we}};
assign debug_wb_rf_wnum = ms_final_result; assign debug_wb_rf_wnum = dest;
assign debug_wb_rf_wdata = ms_final_result; assign debug_wb_rf_wdata = ms_final_result;
endmodule endmodule

2
lacpu/rtl/soc_lite_top.v
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@@ -35,7 +35,7 @@ module soc_lite_top
wire [31:0] cpu_data_rdata; wire [31:0] cpu_data_rdata;
//cpu //cpu
mycpu mycpu( mycpu_top mycpu_top(
.clk (cpu_clk ), .clk (cpu_clk ),
.resetn (cpu_resetn), //low active .resetn (cpu_resetn), //low active

14
lacpu/run_vivado/la32r/la32r.xpr
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@@ -29,7 +29,7 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="WTXSimLaunchSim" Val="35"/> <Option Name="WTXSimLaunchSim" Val="36"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
@@ -145,7 +145,7 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/mycpu.v"> <File Path="$PPRDIR/../../rtl/cpu/mycpu_top.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
@@ -166,6 +166,13 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/tools.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/cpu/wb_stage.v"> <File Path="$PPRDIR/../../rtl/cpu/wb_stage.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -320,7 +327,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/> <Step Id="init_design"/>
@@ -333,7 +340,6 @@
<Step Id="post_route_phys_opt_design"/> <Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/> <Step Id="write_bitstream"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>