diff --git a/lacpu/rtl/cpu/alu.v b/lacpu/rtl/cpu/alu.v index 63724a3..163f842 100755 --- a/lacpu/rtl/cpu/alu.v +++ b/lacpu/rtl/cpu/alu.v @@ -44,9 +44,6 @@ module alu( wire [31:0] sll_result; wire [63:0] sr64_result; wire [31:0] sr_result; - wire [63:0] mul64_result; - wire [63:0] mulu64_result; - wire [31:0] mul_result; // 32-bit adder wire [31:0] adder_a; @@ -77,7 +74,7 @@ module alu( assign or_result = alu_src1 | alu_src2; assign nor_result = ~or_result; assign xor_result = alu_src1 ^ alu_src2; - assign lui_result = {alu_src2[19:0], 12'b0}; + assign lui_result = alu_src2; // SLL result assign sll_result = alu_src1 << alu_src2[4:0]; diff --git a/lacpu/rtl/cpu/exe_stage.v b/lacpu/rtl/cpu/exe_stage.v index c0a58eb..49b59e4 100755 --- a/lacpu/rtl/cpu/exe_stage.v +++ b/lacpu/rtl/cpu/exe_stage.v @@ -1,7 +1,7 @@ module exe_stage #( parameter BR_BUS_WD = 33, - parameter DS_TO_ES_BUS_WD = 206, + parameter DS_TO_ES_BUS_WD = 237, parameter ES_TO_MS_BUS_WD = 175, parameter MS_TO_ES_BUS_WD = 38, parameter WS_TO_ES_BUS_WD = 38 @@ -22,7 +22,7 @@ module exe_stage output [BR_BUS_WD -1:0] br_bus, output data_sram_en, - output [ 7:0] data_sram_we, + output [ 3:0] data_sram_we, output [31:0] data_sram_addr, output [31:0] data_sram_wdata ); @@ -71,32 +71,32 @@ module exe_stage wire data_sram_en_temp; wire stallreq_for_mul_div; - wire [31:0] mul_div_result; + wire [31:0] mul_div_result; // TODO!!! wire [31:0] es_result; wire [31:0] csr_wdata; wire [63:0] csr_bus; - assign {csr_op ,//205:199 - csr_wdata_sel ,//198:198 - csr_addr ,//197:184 - csr_we ,//183:183 - alu_op ,//182:171 - mul_div_op ,//170:167 - mul_div_sign ,//166:166 - branch_op ,//165:157 - store_op ,//156:154 - load_op ,//153:148 - reg_we ,//147:147 - src1_is_pc ,//146:146 - src2_is_imm ,//145:145 - src2_is_4 ,//144:144 - rj ,//143:139 - rkd ,//138:134 - rj_value ,//133:102 - rkd_value ,//101:70 - dest ,//69 :65 + assign {csr_op ,//236:230 + csr_wdata_sel ,//229:229 + csr_addr ,//228:215 + csr_we ,//214:214 + alu_op ,//213:202 + mul_div_op ,//198:189 + mul_div_sign ,//197:197 + branch_op ,//196:188 + store_op ,//187:185 + load_op ,//184:179 + reg_we ,//178:178 + src1_is_pc ,//177:177 + src2_is_imm ,//176:176 + src2_is_4 ,//175:175 + rj ,//174:170 + rkd ,//169:165 + rj_value ,//164:133 + rkd_value ,//132:101 + dest ,//100:96 imm ,//95 :64 es_pc ,//63 :32 inst //31 :0 @@ -176,8 +176,8 @@ module exe_stage wire csr_cancel; wire csr_cancel_reg; - assign csr_cancel = 1'b1; - assign csr_cancel_reg = 1'b1; //TODO! + assign csr_cancel = 1'b0; + assign csr_cancel_reg = 1'b0; //TODO! assign br_bus = {br_taken & ~(csr_cancel|csr_cancel_reg), br_target @@ -186,8 +186,8 @@ module exe_stage lsu u_lsu( .load_op (load_op ), .store_op (store_op ), - .rj_value (rj_value ), - .rkd_value (rkd_value ), + .rj_value (src1 ), + .rkd_value (src2 ), .imm (imm ), .data_sram_en (data_sram_en_temp), diff --git a/lacpu/rtl/cpu/id_stage.v b/lacpu/rtl/cpu/id_stage.v index e6ee87c..2734982 100755 --- a/lacpu/rtl/cpu/id_stage.v +++ b/lacpu/rtl/cpu/id_stage.v @@ -1,7 +1,7 @@ module id_stage #( parameter FS_TO_DS_BUS_WD = 32, - parameter DS_TO_ES_BUS_WD = 206, + parameter DS_TO_ES_BUS_WD = 237, parameter WS_TO_RF_BUS_WD = 38 ) ( @@ -12,7 +12,7 @@ module id_stage input [ 5:0] stall, input br_taken, - output stallreq_id, + output stallreq_ds, input pc_valid, input [31:0] inst_sram_rdata, @@ -62,12 +62,12 @@ module id_stage wire [31:0] inst; wire [31:0] next_inst; - wire rf_raddr1; + wire [ 4:0] rf_raddr1; wire [31:0] rf_rdata1; - wire rf_raddr2; + wire [ 4:0] rf_raddr2; wire [31:0] rf_rdata2; wire rf_we; - wire rf_waddr; + wire [ 4:0] rf_waddr; wire [31:0] rf_wdata; wire [31:0] rj_value; @@ -91,25 +91,25 @@ module id_stage assign csr_vec_l = 0; //TODO! assign csr_vec = {csr_vec_h_r, csr_vec_l}; - assign ds_to_es_bus = {csr_op ,//205:199 - csr_wdata_sel ,//198:198 - csr_addr ,//197:184 - csr_we ,//183:183 - alu_op ,//182:171 - mul_div_op & {4{pc_valid_r}} ,//170:167 - mul_div_sign & pc_valid_r ,//166:166 - branch_op & {9{pc_valid_r}} ,//165:157 - store_op & {3{pc_valid_r}} ,//156:154 - load_op & {6{pc_valid_r}} ,//153:148 - reg_we & pc_valid_r ,//147:147 - src1_is_pc ,//146:146 - src2_is_imm ,//145:145 - src2_is_4 ,//144:144 - rj ,//143:139 - rkd ,//138:134 - rj_value ,//133:102 - rkd_value ,//101:70 - dest ,//69 :65 + assign ds_to_es_bus = {csr_op ,//236:230 + csr_wdata_sel ,//229:229 + csr_addr ,//228:215 + csr_we ,//214:214 + alu_op ,//213:202 + mul_div_op & {4{pc_valid_r}} ,//198:189 + mul_div_sign & pc_valid_r ,//197:197 + branch_op & {9{pc_valid_r}} ,//196:188 + store_op & {3{pc_valid_r}} ,//187:185 + load_op & {6{pc_valid_r}} ,//184:179 + reg_we & pc_valid_r ,//178:178 + src1_is_pc ,//177:177 + src2_is_imm ,//176:176 + src2_is_4 ,//175:175 + rj ,//174:170 + rkd ,//169:165 + rj_value ,//164:133 + rkd_value ,//132:101 + dest ,//100:96 imm ,//95 :64 ds_pc ,//63 :32 inst & {32{pc_valid_r}} //31 :0 @@ -195,7 +195,6 @@ module id_stage .csr_op (csr_op ), .csr_addr (csr_addr ), .csr_wdata_sel (csr_wdata_sel ), - .sel_rf_res (sel_rf_res ), .reg_we (reg_we ) ); @@ -246,7 +245,7 @@ module id_stage //ex段为load指令，且发生数据相关时，id段需要被暂停 assign stallreq_load = ex_is_load & ex_rf_we & ((ex_rf_waddr==rj_value & rj_value!=0)|(ex_rf_waddr==rkd_value & rkd_value!=0)); assign stallreq_csr = ex_is_csr & ex_rf_we & ((ex_rf_waddr==rj_value & rj_value!=0)|(ex_rf_waddr==rkd_value & rkd_value!=0)); - assign stallreq_id = stallreq_load | stallreq_csr; + assign stallreq_ds = stallreq_load | stallreq_csr; endmodule \ No newline at end of file diff --git a/lacpu/rtl/cpu/inst_decoder.v b/lacpu/rtl/cpu/inst_decoder.v index e569ba0..4430218 100644 --- a/lacpu/rtl/cpu/inst_decoder.v +++ b/lacpu/rtl/cpu/inst_decoder.v @@ -1,4 +1,3 @@ -`include "tools.v" module inst_decoder( input [31:0] inst, @@ -31,7 +30,7 @@ module inst_decoder( output csr_wdata_sel, //output [31:0] csr_vec_l, - output [ 3:0] sel_rf_res, + //output [ 3:0] sel_rf_res, output reg_we ); @@ -428,7 +427,7 @@ module inst_decoder( assign csr_op = {inst_csrrd, inst_csrwr, inst_csrxchg, - inst_rdcntid_w, + inst_rdcntid_w, inst_rdcntvh_w, inst_rdcntvl_w, inst_sc_w @@ -439,8 +438,8 @@ module inst_decoder( // rf_res from - assign sel_rf_res[0] = inst_jirl | inst_bl; - assign sel_rf_res[1] = |load_op; - assign sel_rf_res[2] = |csr_op; - assign sel_rf_res[3] = |mul_div_op; + // assign sel_rf_res[0] = inst_jirl | inst_bl; + // assign sel_rf_res[1] = |load_op; + // assign sel_rf_res[2] = |csr_op; + // assign sel_rf_res[3] = |mul_div_op; endmodule diff --git a/lacpu/rtl/cpu/lsu.v b/lacpu/rtl/cpu/lsu.v index 6d68569..fa6eca9 100644 --- a/lacpu/rtl/cpu/lsu.v +++ b/lacpu/rtl/cpu/lsu.v @@ -6,9 +6,9 @@ module lsu( input [31:0] imm, output data_sram_en, - output data_sram_we, - output data_sram_addr, - output data_sram_wdata + output [ 3:0] data_sram_we, + output [31:0] data_sram_addr, + output [31:0] data_sram_wdata ); wire inst_ll_w; wire inst_ld_b; diff --git a/lacpu/rtl/cpu/mem_stage.v b/lacpu/rtl/cpu/mem_stage.v index 6ddcaca..41a604b 100755 --- a/lacpu/rtl/cpu/mem_stage.v +++ b/lacpu/rtl/cpu/mem_stage.v @@ -68,7 +68,7 @@ module mem_stage assign ms_to_es_bus = {reg_we, dest, - es_result + (|load_op) ? ms_result : es_result }; assign ms_to_ws_bus = {reg_we ,//101:101 diff --git a/lacpu/rtl/cpu/mycpu.v b/lacpu/rtl/cpu/mycpu_top.v similarity index 93% rename from lacpu/rtl/cpu/mycpu.v rename to lacpu/rtl/cpu/mycpu_top.v index f5c144e..7b4f0e1 100644 --- a/lacpu/rtl/cpu/mycpu.v +++ b/lacpu/rtl/cpu/mycpu_top.v @@ -1,14 +1,14 @@ -module mycpu +module mycpu_top #( parameter FS_TO_DS_BUS_WD = 32, - parameter DS_TO_ES_BUS_WD = 206, + parameter DS_TO_ES_BUS_WD = 237, parameter ES_TO_MS_BUS_WD = 175, parameter MS_TO_WS_BUS_WD = 102, parameter WS_TO_RF_BUS_WD = 38, - parameter MS_TO_ES_BUS_WD = 32, - parameter WS_TO_ES_BUS_WD = 32, - parameter BR_BUS_WD = 33 + parameter MS_TO_ES_BUS_WD = 38, + parameter WS_TO_ES_BUS_WD = 38, + parameter BR_BUS_WD = 33 ) ( @@ -44,11 +44,14 @@ module mycpu wire [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus; wire [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus; + wire [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus; + wire [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus; + wire [BR_BUS_WD -1:0] br_bus; wire flush; wire stallreq_es; - wire stallreq_id; + wire stallreq_ds; wire [ 5:0] stall; wire except_en; wire [31:0] new_pc; @@ -76,7 +79,7 @@ module mycpu .flush (flush ), .stall (stall ), .br_taken (br_bus[32] ), - .stallreq_id (stallreq_id ), + .stallreq_ds (stallreq_ds ), .fs_to_ds_bus (fs_to_ds_bus ), .pc_valid (inst_sram_en ), .inst_sram_rdata (inst_sram_rdata ), diff --git a/lacpu/rtl/cpu/regfile.v b/lacpu/rtl/cpu/regfile.v index e9ad95b..1353032 100755 --- a/lacpu/rtl/cpu/regfile.v +++ b/lacpu/rtl/cpu/regfile.v @@ -56,13 +56,13 @@ module regfile( end //READ OUT 1 - assign rdata1 = (raddr1==5'b0 ) ? 32'b0 : - (raddr1==waddr) ? wdata : - rf[raddr1]; + assign rdata1 = (raddr1==5'b0 ) ? 32'b0 : + (raddr1==waddr) & we ? wdata : + rf[raddr1]; //READ OUT 2 - assign rdata2 = (raddr2==5'b0 ) ? 32'b0 : - (raddr2==waddr) ? wdata : - rf[raddr2]; + assign rdata2 = (raddr2==5'b0 ) ? 32'b0 : + (raddr2==waddr) & we ? wdata : + rf[raddr2]; endmodule \ No newline at end of file diff --git a/lacpu/rtl/cpu/tools.v b/lacpu/rtl/cpu/tools.v index 234bf1f..b140e32 100755 --- a/lacpu/rtl/cpu/tools.v +++ b/lacpu/rtl/cpu/tools.v @@ -1,3 +1,4 @@ +`default_nettype wire module decoder_2_4( input [ 1:0] in, output [ 3:0] out diff --git a/lacpu/rtl/cpu/wb_stage.v b/lacpu/rtl/cpu/wb_stage.v index 3173862..a4761b3 100755 --- a/lacpu/rtl/cpu/wb_stage.v +++ b/lacpu/rtl/cpu/wb_stage.v @@ -62,7 +62,7 @@ module wb_stage assign debug_wb_pc = ws_pc; assign debug_wb_rf_we = {4{reg_we}}; - assign debug_wb_rf_wnum = ms_final_result; + assign debug_wb_rf_wnum = dest; assign debug_wb_rf_wdata = ms_final_result; endmodule \ No newline at end of file diff --git a/lacpu/rtl/soc_lite_top.v b/lacpu/rtl/soc_lite_top.v index 01ca86e..4b06fe4 100755 --- a/lacpu/rtl/soc_lite_top.v +++ b/lacpu/rtl/soc_lite_top.v @@ -35,7 +35,7 @@ module soc_lite_top wire [31:0] cpu_data_rdata; //cpu - mycpu mycpu( + mycpu_top mycpu_top( .clk (cpu_clk ), .resetn (cpu_resetn), //low active diff --git a/lacpu/run_vivado/la32r/la32r.xpr b/lacpu/run_vivado/la32r/la32r.xpr index e1acad0..76896df 100644 --- a/lacpu/run_vivado/la32r/la32r.xpr +++ b/lacpu/run_vivado/la32r/la32r.xpr @@ -29,7 +29,7 @@