56 lines
1.6 KiB
Verilog
56 lines
1.6 KiB
Verilog
module lsu(
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input [ 5:0] load_op,
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input [ 2:0] store_op,
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input [31:0] rj_value,
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input [31:0] rkd_value,
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input [31:0] imm,
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output data_sram_en,
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output [ 3:0] data_sram_we,
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output [31:0] data_sram_addr,
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output [31:0] data_sram_wdata
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);
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wire inst_ll_w;
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wire inst_ld_b;
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wire inst_ld_bu;
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wire inst_ld_h;
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wire inst_ld_hu;
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wire inst_ld_w;
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wire inst_st_b;
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wire inst_st_h;
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wire inst_st_w;
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wire [31:0] addr;
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wire [ 3:0] byte_sel;
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assign {inst_ld_b,
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inst_ld_h,
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inst_ld_w,
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inst_ld_bu,
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inst_ld_hu,
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inst_ll_w
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} = load_op;
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assign {inst_st_b,
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inst_st_h,
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inst_st_w
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} = store_op;
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assign addr = rj_value + imm;
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decoder_2_4 u_decoder_2_4(
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.in (addr[1:0]),
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.out(byte_sel )
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);
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assign data_sram_en = (|store_op) | (|load_op);
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assign data_sram_we = inst_st_b ? byte_sel :
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inst_st_h ? {{2{byte_sel[2]}}, {2{byte_sel[0]}}} :
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inst_st_w ? { 4{byte_sel[0]}} :
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4'b0;
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assign data_sram_addr = addr;
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assign data_sram_wdata = inst_st_b ? {4{rkd_value[ 7:0]}} :
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inst_st_h ? {2{rkd_value[15:0]}} :
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inst_st_w ? rkd_value :
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32'b0;
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endmodule |