FPGALab/ddr3_general_design
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5dd963dd126c62d03bc8a18b9517359dd4238748
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UnbalancedCat 5dd963dd12 fix gitignore
2025-03-18 12:13:58 +08:00
ddr_general_design.srcs/sources_1
fix gitignore
2025-03-18 12:13:58 +08:00
others
add axi
2025-03-18 12:11:59 +08:00
.gitignore
fix gitignore
2025-03-18 12:13:58 +08:00
ddr_general_design.xpr
add axi
2025-03-18 12:11:59 +08:00
Description
基于 ax7325t 的通用 axi 转 fifo 的 mig ddr3 控制接口项目模板
59 MiB
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Verilog 100%