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###############################################################################

##   ____  ____

##  /   /\/   /

## /___/  \  /    Vendor             : Xilinx

## \   \   \/     Version            : 4.2

##  \   \         Application        : MIG

##  /   /         Filename           : ies_run.sh

## /___/   /\     Date Last Modified : $Date: 2011/06/02 08:31:17 $

## \   \  /  \    Date Created       : Tue Oct 29 2013

##  \___\/\___\

##

## Device           : 7 Series

## Purpose          :

##                   Sample ies_run.sh file to compile and simulate memory interface

##                   design and run the simulation for specified period of time.

##                   Display the waveforms that are listed with "add wave" command.

## Assumptions      :

##                   Simulation takes place in \sim folder of MIG output directory.

## Reference        :

## Revision History :

###############################################################################



#echo Simulation Tool: IES



#Compile the required libraries here#

#libraries path#



#Compile all modules#

ncvlog -work worklib -sv -messages mig_7series*.v > ies_sim.log

ncvlog -sv -work worklib -messages ../pcie_ddr_mig_7series_0_0_ex.srcs/sources_1/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0.v >> ies_sim.log

ncvlog -sv -work worklib -messages ../pcie_ddr_mig_7series_0_0_ex.srcs/sources_1/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/pcie_ddr_mig_7series_0_0_mig_sim.v >> ies_sim.log

ncvlog -work worklib -messages -sv ../pcie_ddr_mig_7series_0_0_ex.srcs/sources_1/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/clocking/*.v >> ies_sim.log

ncvlog -work worklib -messages -sv ../pcie_ddr_mig_7series_0_0_ex.srcs/sources_1/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/controller/*.v >> ies_sim.log

ncvlog -work worklib -messages -sv ../pcie_ddr_mig_7series_0_0_ex.srcs/sources_1/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/ecc/*.v >> ies_sim.log

ncvlog -work worklib -messages -sv ../pcie_ddr_mig_7series_0_0_ex.srcs/sources_1/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/ip_top/*.v >> ies_sim.log

ncvlog -work worklib -messages -sv ../pcie_ddr_mig_7series_0_0_ex.srcs/sources_1/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/phy/*.v >> ies_sim.log

ncvlog -work worklib -messages -sv ../pcie_ddr_mig_7series_0_0_ex.srcs/sources_1/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/ui/*.v >> ies_sim.log

ncvlog -sv -work worklib -messages ../pcie_ddr_mig_7series_0_0_ex.srcs/sources_1/ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0/user_design/rtl/axi/*.v >> ies_sim.log 





ncvlog -sv -work worklib -messages example_top.v >> ies_sim.log



#Compile files in sim folder (excluding model parameter file)#

#$XILINX variable must be set

ncvlog -work worklib -messages $XILINX_VIVADO/data/verilog/src/glbl.v >> ies_sim.log

ncvlog -work worklib -messages wiredly.v >> ies_sim.log

ncvlog -work worklib -messages sim_tb_top.v >> ies_sim.log



#Pass the parameters for memory model parameter file#

ncvlog -work worklib -messages -sv +define+x4Gb +define+sg15E +define+x8 ddr3_model.sv >> ies_sim.log 



#Simulate the design with sim_tb_top as the top module

ncelab -namemap_mixgen -timescale '1ps/1ps' -vhdlsync -v93 -messages -nettype_port_relax -access +rwc sim_tb_top glbl >> ies_sim.log

ncsim sim_tb_top >> ies_sim.log

#echo done



