FPGALab/ddr3_general_design
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包焕垲
2025-03-24 11:35:28 +08:00
parent 630b6e313a
commit e72b563b6e
283 changed files with 3083819 additions and 27186 deletions
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ddr_general_design.xpr
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@@ -36,13 +36,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="22"/>
<Option Name="WTModelSimExportSim" Val="22"/>
<Option Name="WTQuestaExportSim" Val="22"/>
<Option Name="WTIesExportSim" Val="22"/>
<Option Name="WTVcsExportSim" Val="22"/>
<Option Name="WTRivieraExportSim" Val="22"/>
<Option Name="WTActivehdlExportSim" Val="22"/>
<Option Name="WTXSimExportSim" Val="26"/>
<Option Name="WTModelSimExportSim" Val="26"/>
<Option Name="WTQuestaExportSim" Val="26"/>
<Option Name="WTIesExportSim" Val="26"/>
<Option Name="WTVcsExportSim" Val="26"/>
<Option Name="WTRivieraExportSim" Val="26"/>
<Option Name="WTActivehdlExportSim" Val="26"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -58,6 +58,50 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/bd/pcie_ddr/pcie_ddr.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="pcie_ddr.bd" FileRelPathName="ip/pcie_ddr_auto_us_0/pcie_ddr_auto_us_0.xci">
<Proxy FileSetName="pcie_ddr_auto_us_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pcie_ddr.bd" FileRelPathName="ip/pcie_ddr_util_ds_buf_0_0/pcie_ddr_util_ds_buf_0_0.xci">
<Proxy FileSetName="pcie_ddr_util_ds_buf_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pcie_ddr.bd" FileRelPathName="ip/pcie_ddr_clk_wiz_0_0/pcie_ddr_clk_wiz_0_0.xci">
<Proxy FileSetName="pcie_ddr_clk_wiz_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pcie_ddr.bd" FileRelPathName="ip/pcie_ddr_xdma_0_0/pcie_ddr_xdma_0_0.xci">
<Proxy FileSetName="pcie_ddr_xdma_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pcie_ddr.bd" FileRelPathName="ip/pcie_ddr_xbar_3/pcie_ddr_xbar_3.xci">
<Proxy FileSetName="pcie_ddr_xbar_3"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pcie_ddr.bd" FileRelPathName="ip/pcie_ddr_auto_cc_0/pcie_ddr_auto_cc_0.xci">
<Proxy FileSetName="pcie_ddr_auto_cc_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pcie_ddr.bd" FileRelPathName="ip/pcie_ddr_auto_cc_1/pcie_ddr_auto_cc_1.xci">
<Proxy FileSetName="pcie_ddr_auto_cc_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pcie_ddr.bd" FileRelPathName="ip/pcie_ddr_rst_mig_7series_0_100M_8/pcie_ddr_rst_mig_7series_0_100M_8.xci">
<Proxy FileSetName="pcie_ddr_rst_mig_7series_0_100M_8"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pcie_ddr.bd" FileRelPathName="ip/pcie_ddr_mig_7series_0_0/pcie_ddr_mig_7series_0_0.xci">
<Proxy FileSetName="pcie_ddr_mig_7series_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="pcie_ddr.bd" FileRelPathName="ip/pcie_ddr_util_vector_logic_0_0/pcie_ddr_util_vector_logic_0_0.xci">
<Proxy FileSetName="pcie_ddr_util_vector_logic_0_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/axi_fifo_ctrl.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/axi_m_rd.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -72,22 +116,21 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/axi_ddr_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/pcie_ddr/pcie_ddr.bd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/pcie_ddr/hdl/pcie_ddr_wrapper.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/pcie_ddr_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/axi_ddr_top.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -101,29 +144,15 @@
<Attr Name="ScopedToCell" Val="pcie_ddr_mig_7series_0_0"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/pcie_ddr/ip/pcie_ddr_mig_7series_0_0/mig_b.prj">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="ScopedToCell" Val="pcie_ddr_mig_7series_0_0"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/ip/ddr_ctrl/mig_a.prj">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="ScopedToCell" Val="ddr_ctrl"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/axi_fifo_ctrl.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_ddr_top"/>
<Option Name="TopModule" Val="pcie_ddr_top"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
@@ -136,7 +165,7 @@
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="pcie_ddr_wrapper"/>
<Option Name="TopModule" Val="axi_ddr_top"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
@@ -180,6 +209,7 @@
<FileSet Name="ddr_ctrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ddr_ctrl">
<File Path="$PSRCDIR/sources_1/ip/ddr_ctrl/ddr_ctrl.xci">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -229,6 +259,66 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pcie_ddr_xbar_3" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pcie_ddr_xbar_3">
<Config>
<Option Name="TopModule" Val="pcie_ddr_xbar_3"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pcie_ddr_xdma_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pcie_ddr_xdma_0_0">
<Config>
<Option Name="TopModule" Val="pcie_ddr_xdma_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pcie_ddr_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pcie_ddr_clk_wiz_0_0">
<Config>
<Option Name="TopModule" Val="pcie_ddr_clk_wiz_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pcie_ddr_util_ds_buf_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pcie_ddr_util_ds_buf_0_0">
<Config>
<Option Name="TopModule" Val="pcie_ddr_util_ds_buf_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pcie_ddr_auto_us_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pcie_ddr_auto_us_0">
<Config>
<Option Name="TopModule" Val="pcie_ddr_auto_us_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pcie_ddr_auto_cc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pcie_ddr_auto_cc_0">
<Config>
<Option Name="TopModule" Val="pcie_ddr_auto_cc_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pcie_ddr_auto_cc_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pcie_ddr_auto_cc_1">
<Config>
<Option Name="TopModule" Val="pcie_ddr_auto_cc_1"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pcie_ddr_rst_mig_7series_0_100M_8" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pcie_ddr_rst_mig_7series_0_100M_8">
<Config>
<Option Name="TopModule" Val="pcie_ddr_rst_mig_7series_0_100M_8"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pcie_ddr_mig_7series_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pcie_ddr_mig_7series_0_0">
<Config>
<Option Name="TopModule" Val="pcie_ddr_mig_7series_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="pcie_ddr_util_vector_logic_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pcie_ddr_util_vector_logic_0_0">
<Config>
<Option Name="TopModule" Val="pcie_ddr_util_vector_logic_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@@ -249,11 +339,12 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="11">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
@@ -299,6 +390,66 @@
<RQSFiles/>
</Run>
<Run Id="fifo_ddr_len_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_len" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_len" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_len_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="fifo_ddr_mask_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_mask" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_mask" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_mask_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pcie_ddr_xbar_3_synth_1" Type="Ft3:Synth" SrcSet="pcie_ddr_xbar_3" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_xbar_3" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pcie_ddr_xbar_3_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pcie_ddr_xdma_0_0_synth_1" Type="Ft3:Synth" SrcSet="pcie_ddr_xdma_0_0" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_xdma_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pcie_ddr_xdma_0_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pcie_ddr_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="pcie_ddr_clk_wiz_0_0" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pcie_ddr_clk_wiz_0_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pcie_ddr_util_ds_buf_0_0_synth_1" Type="Ft3:Synth" SrcSet="pcie_ddr_util_ds_buf_0_0" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_util_ds_buf_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pcie_ddr_util_ds_buf_0_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pcie_ddr_auto_us_0_synth_1" Type="Ft3:Synth" SrcSet="pcie_ddr_auto_us_0" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_auto_us_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pcie_ddr_auto_us_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
@@ -310,7 +461,55 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="fifo_ddr_mask_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_mask" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_mask" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_mask_synth_1" IncludeInArchive="true">
<Run Id="pcie_ddr_auto_cc_0_synth_1" Type="Ft3:Synth" SrcSet="pcie_ddr_auto_cc_0" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_auto_cc_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pcie_ddr_auto_cc_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pcie_ddr_auto_cc_1_synth_1" Type="Ft3:Synth" SrcSet="pcie_ddr_auto_cc_1" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_auto_cc_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pcie_ddr_auto_cc_1_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pcie_ddr_rst_mig_7series_0_100M_8_synth_1" Type="Ft3:Synth" SrcSet="pcie_ddr_rst_mig_7series_0_100M_8" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_rst_mig_7series_0_100M_8" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pcie_ddr_rst_mig_7series_0_100M_8_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pcie_ddr_mig_7series_0_0_synth_1" Type="Ft3:Synth" SrcSet="pcie_ddr_mig_7series_0_0" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_mig_7series_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pcie_ddr_mig_7series_0_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="pcie_ddr_util_vector_logic_0_0_synth_1" Type="Ft3:Synth" SrcSet="pcie_ddr_util_vector_logic_0_0" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_util_vector_logic_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pcie_ddr_util_vector_logic_0_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
@@ -408,6 +607,108 @@
<RQSFiles/>
</Run>
<Run Id="fifo_ddr_len_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_len" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_len_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design" EnableStepBool="1"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="fifo_ddr_mask_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_mask" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_mask_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Step Id="write_bitstream"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Run Id="pcie_ddr_xbar_3_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_xbar_3" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pcie_ddr_xbar_3_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
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<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Run Id="pcie_ddr_clk_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_clk_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pcie_ddr_clk_wiz_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Step Id="phys_opt_design" EnableStepBool="1"/>
<Step Id="route_design"/>
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<Step Id="write_bitstream"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
<Step Id="route_design"/>
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<Step Id="write_bitstream"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
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<Run Id="pcie_ddr_auto_us_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_auto_us_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pcie_ddr_auto_us_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
@@ -426,7 +727,83 @@
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<Run Id="fifo_ddr_mask_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_mask" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_mask_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Run Id="pcie_ddr_auto_cc_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_auto_cc_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pcie_ddr_auto_cc_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Desc>Default settings for Implementation.</Desc>
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<Step Id="post_route_phys_opt_design"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
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<Run Id="pcie_ddr_auto_cc_1_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_auto_cc_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pcie_ddr_auto_cc_1_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Step Id="route_design"/>
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<Step Id="write_bitstream"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Run Id="pcie_ddr_rst_mig_7series_0_100M_8_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_rst_mig_7series_0_100M_8" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pcie_ddr_rst_mig_7series_0_100M_8_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
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<Desc>Default settings for Implementation.</Desc>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Run Id="pcie_ddr_mig_7series_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="pcie_ddr_mig_7series_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pcie_ddr_mig_7series_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Desc>Default settings for Implementation.</Desc>