FPGALab/ddr3_general_design
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UnbalancedCat e72b563b6e v1.0
2025-03-24 11:35:28 +08:00
ddr_general_design.srcs/sources_1
v1.0
2025-03-24 11:35:28 +08:00
others
v1.0
2025-03-24 11:35:28 +08:00
.gitignore
fix gitignore
2025-03-18 12:13:58 +08:00
ddr_general_design.xpr
v1.0
2025-03-24 11:35:28 +08:00
Description
基于 ax7325t 的通用 axi 转 fifo 的 mig ddr3 控制接口项目模板
59 MiB
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Verilog 100%