FPGALab/ddr3_general_design
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包焕垲
2025-03-24 11:35:28 +08:00
parent 630b6e313a
commit e72b563b6e
283 changed files with 3083819 additions and 27186 deletions
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206
ddr_general_design.srcs/sources_1/new/axi_ddr_top.v
View File

@@ -42,7 +42,23 @@ module axi_ddr_top(
// Single-ended system clock
input sys_clk_i,
input sys_rst_i,
output init_calib_complete
output init_calib_complete,
// Application interface ports
input [1:0] rw_req_i,
input [32:0] rw_addr_i,
input [4:0] rd_len_i,
input [511:0] wr_data_i,
input [63:0] wr_mask_i,
input [4:0] rw_info_i,
output rw_ack_o,
output [4:0] rw_info_o,
output [511:0] rd_data_o,
output rd_data_v_o,
output [4:0] rd_info_o,
output [1:0] rw_fifo_busy_o
);
// Wire declarations
@@ -62,7 +78,7 @@ module axi_ddr_top(
wire s_axi_awvalid;
wire s_axi_awready;
// Slave Interface Write Data Ports
wire [512:0] s_axi_wdata;
wire [511:0] s_axi_wdata;
wire [63:0] s_axi_wstrb;
wire s_axi_wlast;
wire s_axi_wvalid;
@@ -91,22 +107,53 @@ module axi_ddr_top(
wire s_axi_rlast;
wire s_axi_rvalid;
wire rd_fifo_we;
wire rd_fifo_re;
wire [ 7:0] rd_fifo_len;
wire [32:0] rd_fifo_addr;
wire rd_fifo_data_we;
wire rd_fifo_data_re;
wire [511:0] rd_fifo_data_din;
wire [511:0] rd_fifo_data_dout;
wire rd_fifo_data_dout_v;
wire [ 7:0] rd_fifo_len_din;
wire [ 7:0] rd_fifo_len_dout;
wire [32:0] rd_fifo_addr_din;
wire [32:0] rd_fifo_addr_out;
wire [4:0] rd_fifo_info_din;
wire [4:0] rd_fifo_info_dout;
wire rd_fifo_len_empty;
wire rd_fifo_addr_empty;
wire [511:0] rd_fifo_data;
wire rd_fifo_we;
wire rd_fifo_almost_full;
wire rd_fifo_info_empty;
wire rd_fifo_data_empty;
wire rd_fifo_data_full;
wire rd_fifo_data_prog_full;
wire rd_fifo_addr_full;
wire rd_fifo_len_full;
wire rd_fifo_info_full;
wire rd_fifo_data_almost_full;
wire rd_fifo_addr_almost_full;
wire rd_fifo_len_almost_full;
wire rd_fifo_info_almost_full;
wire wr_fifo_re;
wire [32:0] wr_fifo_addr;
wire [511:0] wr_fifo_data;
wire [63:0] wr_fifo_mask;
wire [32:0] wr_fifo_addr_din;
wire [511:0] wr_fifo_data_din;
wire [63:0] wr_fifo_mask_din;
wire [32:0] wr_fifo_addr_dout;
wire [511:0] wr_fifo_data_dout;
wire [63:0] wr_fifo_mask_dout;
wire wr_fifo_addr_empty;
wire wr_fifo_data_empty;
wire wr_fifo_mask_empty;
wire wr_fifo_we;
wire wr_fifo_addr_full;
wire wr_fifo_data_full;
wire wr_fifo_mask_full;
wire wr_fifo_addr_almost_full;
wire wr_fifo_data_almost_full;
wire wr_fifo_mask_almost_full;
ddr_ctrl u_ddr_ctrl(
// Memory interface ports
@@ -132,7 +179,7 @@ ddr_ctrl u_ddr_ctrl(
.ui_clk (ui_clk), // 100 Mhz
.ui_clk_sync_rst (ui_rst),
.mmcm_locked (),
.aresetn (),
.aresetn (~ui_rst),
.app_sr_req (1'b0),
.app_ref_req (1'b0),
.app_zq_req (1'b0),
@@ -192,6 +239,53 @@ ddr_ctrl u_ddr_ctrl(
.sys_rst (sys_rst_i)
);
axi_fifo_ctrl u_axi_fifo_ctrl (
.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i),
.rw_req_i (rw_req_i ),
.rw_addr_i (rw_addr_i ),
.rd_len_i (rd_len_i ),
.wr_data_i (wr_data_i ),
.wr_mask_i (wr_mask_i ),
.rw_info_i (rw_info_i ),
.rw_ack_o (rw_ack_o ),
.rw_info_o (rw_info_o ),
.rd_data_o (rd_data_o ),
.rd_data_v_o (rd_data_v_o),
.rd_info_o (rd_info_o ),
.wr_fifo_almost_full_i(wr_fifo_addr_almost_full & wr_fifo_data_almost_full & wr_fifo_mask_almost_full),
.wr_fifo_full_i(wr_fifo_addr_full & wr_fifo_data_full & wr_fifo_mask_full),
.wr_fifo_we_o(wr_fifo_we),
.wr_fifo_addr_o(wr_fifo_addr_din),
.wr_fifo_data_o(wr_fifo_data_din),
.wr_fifo_mask_o(wr_fifo_mask_din),
.rd_fifo_almost_full_i(rd_fifo_addr_almost_full & rd_fifo_len_almost_full & rd_fifo_info_almost_full),
.rd_fifo_full_i(rd_fifo_addr_full & rd_fifo_len_full & rd_fifo_info_full),
.rd_fifo_addr_o(rd_fifo_addr_din),
.rd_fifo_len_o(rd_fifo_len_din),
.rd_fifo_info_o(rd_fifo_info_din),
.rd_fifo_we_o(rd_fifo_we),
.rd_fifo_empty_i(rd_fifo_addr_empty & rd_fifo_len_empty & rd_fifo_info_empty),
.rd_fifo_re_o(rd_fifo_data_re),
.rd_fifo_data_i(rd_fifo_data_dout),
.rd_fifo_data_v_i(rd_fifo_data_dout_v),
.rd_fifo_info_i(rd_fifo_info_dout),
.rw_fifo_busy_o(rw_fifo_busy_o)
);
// Instance of axi_m_rd
axi_m_rd u_axi_m_rd (
.ui_clk_i(ui_clk),
@@ -218,11 +312,11 @@ axi_m_rd u_axi_m_rd (
// Remaining ports
.rd_fifo_empty_i(rd_fifo_addr_empty & rd_fifo_len_empty),
.rd_fifo_re_o(rd_fifo_re),
.rd_fifo_addr_i(rd_fifo_addr),
.rd_fifo_len_i(rd_fifo_len),
.rd_fifo_almost_full_i(rd_fifo_almost_full),
.rd_fifo_we_o(rd_fifo_we),
.rd_fifo_din_o(rd_fifo_data)
.rd_fifo_addr_i(rd_fifo_addr_dout),
.rd_fifo_len_i(rd_fifo_len_dout),
.rd_fifo_almost_full_i(rd_fifo_data_almost_full),
.rd_fifo_we_o(rd_fifo_data_we),
.rd_fifo_din_o(rd_fifo_data_din)
);
@@ -230,49 +324,54 @@ axi_m_rd u_axi_m_rd (
fifo_ddr_addr fifo_rd_addr_inst(
.rst(sys_rst_i),
.wr_clk(sys_clk_i),
.wr_en(),
.din(),
.full(),
.wr_en(rd_fifo_we),
.din(rd_fifo_addr_din),
.full(rd_fifo_addr_full),
.almost_full(rd_fifo_addr_almost_full),
.rd_clk(ui_clk),
.rd_en(rd_fifo_re),
.dout(rd_fifo_addr),
.dout(rd_fifo_addr_dout),
.empty(rd_fifo_addr_empty)
);
fifo_ddr_len fifo_rd_len_inst(
.rst(sys_rst_i),
.wr_clk(sys_clk_i),
.wr_en(),
.din(),
.full(),
.wr_en(rd_fifo_we),
.din(rd_fifo_len_din),
.full(rd_fifo_len_full),
.almost_full(rd_fifo_len_almost_full),
.rd_clk(ui_clk),
.rd_en(rd_fifo_re),
.dout(rd_fifo_len),
.dout(rd_fifo_len_dout),
.empty(rd_fifo_len_empty)
);
fifo_ddr_data fifo_rd_data_inst(
.rst(ui_rst),
.wr_clk(ui_clk),
.wr_en(rd_fifo_we),
.din(rd_fifo_data),
.almost_full(rd_fifo_almost_full),
.full(),
.wr_en(rd_fifo_data_we),
.din(rd_fifo_data_din),
.almost_full(rd_fifo_data_almost_full),
.full(rd_fifo_data_full),
.prog_full(rd_fifo_data_prog_full),
.rd_clk(sys_clk_i),
.rd_en(),
.dout(),
.empty()
.rd_en(rd_fifo_data_re),
.dout(rd_fifo_data_dout),
.empty(rd_fifo_data_empty),
.valid(rd_fifo_data_dout_v)
);
fifo_ddr_info fifo_rd_info_inst(
.srst(sys_rst_i),
.clk(sys_clk_i),
.wr_en(),
.din(),
.full(),
.rd_en(),
.dout(),
.empty()
.wr_en(rd_fifo_we),
.din(rd_fifo_info_din),
.full(rd_fifo_info_full),
.almost_full(rd_fifo_info_almost_full),
.rd_en(rd_fifo_re),
.dout(rd_fifo_info_dout),
.empty(rd_fifo_info_empty)
);
// Instance of axi_m_wr
@@ -304,45 +403,48 @@ axi_m_wr u_axi_m_wr (
// Remaining ports
.wr_fifo_empty_i(wr_fifo_addr_empty && wr_fifo_data_empty && wr_fifo_mask_empty),
.wr_fifo_re_o(wr_fifo_re),
.wr_fifo_addr_i(wr_fifo_addr),
.wr_fifo_addr_i(wr_fifo_addr_dout),
.wr_fifo_len_i(1'b1),
.wr_fifo_data_i(wr_fifo_data),
.wr_fifo_mask_i(wr_fifo_mask)
.wr_fifo_data_i(wr_fifo_data_dout),
.wr_fifo_mask_i(wr_fifo_mask_dout)
);
fifo_ddr_addr fifo_wr_addr_inst(
.rst(sys_rst_i),
.wr_clk(sys_clk_i),
.wr_en(),
.din(),
.full(),
.wr_en(wr_fifo_we),
.din(wr_fifo_addr_din),
.full(wr_fifo_addr_full),
.almost_full(wr_fifo_addr_almost_full),
.rd_clk(ui_clk),
.rd_en(wr_fifo_re),
.dout(wr_fifo_addr),
.dout(wr_fifo_addr_dout),
.empty(wr_fifo_addr_empty)
);
fifo_ddr_data fifo_wr_data_inst(
.rst(sys_rst_i),
.wr_clk(sys_clk_i),
.wr_en(),
.din(),
.full(),
.wr_en(wr_fifo_we),
.din(wr_fifo_data_din),
.full(wr_fifo_data_full),
.almost_full(wr_fifo_data_almost_full),
.rd_clk(ui_clk),
.rd_en(wr_fifo_re),
.dout(wr_fifo_data),
.dout(wr_fifo_data_dout),
.empty(wr_fifo_data_empty)
);
fifo_ddr_mask fifo_wr_mask_inst(
.rst(sys_rst_i),
.wr_clk(sys_clk_i),
.wr_en(),
.din(),
.full(),
.wr_en(wr_fifo_we),
.din(wr_fifo_mask_din),
.full(wr_fifo_mask_full),
.almost_full(wr_fifo_mask_almost_full),
.rd_clk(ui_clk),
.rd_en(wr_fifo_re),
.dout(wr_fifo_mask),
.dout(wr_fifo_mask_dout),
.empty(wr_fifo_mask_empty)
);

33
ddr_general_design.srcs/sources_1/new/axi_fifo_ctrl.v
View File

@@ -53,8 +53,8 @@ module axi_fifo_ctrl(
output rd_fifo_we_o,
input rd_fifo_empty_i,
output rd_fifo_re_o,
input [511:0] rd_fifo_data_o,
input rd_fifo_data_v_o,
input [511:0] rd_fifo_data_i,
input rd_fifo_data_v_i,
input [4:0] rd_fifo_info_i,
output [1:0] rw_fifo_busy_o
@@ -102,7 +102,7 @@ module axi_fifo_ctrl(
assign rd_fifo_we_o = rd_fifo_we;
assign rd_fifo_re_o = rd_fifo_re;
assign rd_fifo_info_o = rw_info;
assign rw_fifo_busy_o = 2'b11; // !
assign rw_fifo_busy_o = {rd_fifo_full_i, wr_fifo_full_i}; // !
always @(posedge sys_clk_i or posedge sys_rst_i) begin
if (sys_rst_i) begin
@@ -124,7 +124,6 @@ module axi_fifo_ctrl(
rd_fifo_addr = 33'b0;
rd_fifo_len = 8'b0;
rd_fifo_we = 1'b0;
rd_fifo_re = 1'b0;
n_state = S_IDLE;
case (c_state)
S_IDLE: begin
@@ -188,15 +187,31 @@ module axi_fifo_ctrl(
endcase
end
reg c_state_rd;
reg n_state_rd;
localparam
S_IDLE_RD = 3'b000,
S_RD_START_RD = 3'b001,
S_RD_RESP_RD = 3'b010;
always @(posedge sys_clk_i or posedge sys_rst_i) begin
if (sys_rst_i) begin
rd_data <= 512'b0;
rd_data_v <= 1'b0;
rd_info <= 5'b0;
rd_data <= 512'b0;
rd_data_v <= 1'b0;
rd_info <= 5'b0;
rd_fifo_re <= 1'b0;
end
else begin
if () begin
rd_data <= rd_fifo_data_i;
rd_data_v <= rd_fifo_data_v_i;
rd_info <= rd_fifo_info_i;
if (!rd_fifo_empty_i) begin
rd_fifo_re <= 1'b1;
end
else begin
rd_fifo_re <= 1'b0;
end
end
end

392
ddr_general_design.srcs/sources_1/new/pcie_ddr_top.v Normal file
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@@ -0,0 +1,392 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/24 10:22:00
// Design Name:
// Module Name: pcie_ddr_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pcie_ddr_top(
output [15:0]ddr_addr,
output [2:0]ddr_ba,
output ddr_cas_n,
output [1:0]ddr_ck_n,
output [1:0]ddr_ck_p,
output [1:0]ddr_cke,
output [1:0]ddr_cs_n,
output [7:0]ddr_dm,
inout [63:0]ddr_dq,
inout [7:0]ddr_dqs_n,
inout [7:0]ddr_dqs_p,
output [1:0]ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_we_n,
output init_calib_complete,
input [0:0]pcie_clk_clk_n,
input [0:0]pcie_clk_clk_p,
input [7:0]pcie_mgt_rxn,
input [7:0]pcie_mgt_rxp,
output [7:0]pcie_mgt_txn,
output [7:0]pcie_mgt_txp,
output pcie_msi_enable,
output pcie_user_lnk_up,
input [0:0]pcie_usr_irq_req,
input sys_clk_i,
input sys_rst_i,
input [1:0] rw_req_i,
input [32:0] rw_addr_i,
input [4:0] rd_len_i,
input [511:0] wr_data_i,
input [63:0] wr_mask_i,
input [4:0] rw_info_i,
output rw_ack_o,
output [4:0] rw_info_o,
output [511:0] rd_data_o,
output rd_data_v_o,
output [4:0] rd_info_o,
output [1:0] rw_fifo_busy_o
);
pcie_ddr_wrapper u_pcie_ddr_wrapper(
.ddr_addr (ddr_addr ),
.ddr_axi_araddr (s_axi_araddr ),
.ddr_axi_arburst (s_axi_arburst ),
.ddr_axi_arcache (s_axi_arcache ),
.ddr_axi_arid (s_axi_arid ),
.ddr_axi_arlen (s_axi_arlen ),
.ddr_axi_arlock (s_axi_arlock ),
.ddr_axi_arprot (s_axi_arprot ),
.ddr_axi_arqos (s_axi_arqos ),
.ddr_axi_arready (s_axi_arready ),
.ddr_axi_arregion (s_axi_arregion ),
.ddr_axi_arsize (s_axi_arsize ),
.ddr_axi_arvalid (s_axi_arvalid ),
.ddr_axi_awaddr (s_axi_awaddr ),
.ddr_axi_awburst (s_axi_awburst ),
.ddr_axi_awcache (s_axi_awcache ),
.ddr_axi_awid (s_axi_awid ),
.ddr_axi_awlen (s_axi_awlen ),
.ddr_axi_awlock (s_axi_awlock ),
.ddr_axi_awprot (s_axi_awprot ),
.ddr_axi_awqos (s_axi_awqos ),
.ddr_axi_awready (s_axi_awready ),
.ddr_axi_awregion (s_axi_awregion ),
.ddr_axi_awsize (s_axi_awsize ),
.ddr_axi_awvalid (s_axi_awvalid ),
.ddr_axi_bid (s_axi_bid ),
.ddr_axi_bready (s_axi_bready ),
.ddr_axi_bresp (s_axi_bresp ),
.ddr_axi_bvalid (s_axi_bvalid ),
.ddr_axi_rdata (s_axi_rdata ),
.ddr_axi_rid (s_axi_rid ),
.ddr_axi_rlast (s_axi_rlast ),
.ddr_axi_rready (s_axi_rready ),
.ddr_axi_rresp (s_axi_rresp ),
.ddr_axi_rvalid (s_axi_rvalid ),
.ddr_axi_wdata (s_axi_wdata ),
.ddr_axi_wlast (s_axi_wlast ),
.ddr_axi_wready (s_axi_wready ),
.ddr_axi_wstrb (s_axi_wstrb ),
.ddr_axi_wvalid (s_axi_wvalid ),
.ddr_ba (ddr_ba ),
.ddr_cas_n (ddr_cas_n ),
.ddr_ck_n (ddr_ck_n ),
.ddr_ck_p (ddr_ck_p ),
.ddr_cke (ddr_cke ),
.ddr_cs_n (ddr_cs_n ),
.ddr_dm (ddr_dm ),
.ddr_dq (ddr_dq ),
.ddr_dqs_n (ddr_dqs_n ),
.ddr_dqs_p (ddr_dqs_p ),
.ddr_odt (ddr_odt ),
.ddr_ras_n (ddr_ras_n ),
.ddr_reset_n (ddr_reset_n ),
.ddr_we_n (ddr_we_n ),
.init_calib_complete (init_calib_complete),
.pcie_clk_clk_n (pcie_clk_clk_n ),
.pcie_clk_clk_p (pcie_clk_clk_p ),
.pcie_mgt_rxn (pcie_mgt_rxn ),
.pcie_mgt_rxp (pcie_mgt_rxp ),
.pcie_mgt_txn (pcie_mgt_txn ),
.pcie_mgt_txp (pcie_mgt_txp ),
.pcie_msi_enable (pcie_msi_enable ),
.pcie_user_lnk_up (pcie_user_lnk_up ),
.pcie_usr_irq_req (pcie_usr_irq_req ),
.sys_clk (sys_clk_i ),
.sys_rst (sys_rst_i )
);
wire rd_fifo_we;
wire rd_fifo_re;
wire rd_fifo_data_we;
wire rd_fifo_data_re;
wire [511:0] rd_fifo_data_din;
wire [511:0] rd_fifo_data_dout;
wire rd_fifo_data_dout_v;
wire [ 7:0] rd_fifo_len_din;
wire [ 7:0] rd_fifo_len_dout;
wire [32:0] rd_fifo_addr_din;
wire [32:0] rd_fifo_addr_out;
wire [4:0] rd_fifo_info_din;
wire [4:0] rd_fifo_info_dout;
wire rd_fifo_len_empty;
wire rd_fifo_addr_empty;
wire rd_fifo_info_empty;
wire rd_fifo_data_empty;
wire rd_fifo_data_full;
wire rd_fifo_data_prog_full;
wire rd_fifo_addr_full;
wire rd_fifo_len_full;
wire rd_fifo_info_full;
wire rd_fifo_data_almost_full;
wire rd_fifo_addr_almost_full;
wire rd_fifo_len_almost_full;
wire rd_fifo_info_almost_full;
wire wr_fifo_re;
wire [32:0] wr_fifo_addr_din;
wire [511:0] wr_fifo_data_din;
wire [63:0] wr_fifo_mask_din;
wire [32:0] wr_fifo_addr_dout;
wire [511:0] wr_fifo_data_dout;
wire [63:0] wr_fifo_mask_dout;
wire wr_fifo_addr_empty;
wire wr_fifo_data_empty;
wire wr_fifo_mask_empty;
wire wr_fifo_we;
wire wr_fifo_addr_full;
wire wr_fifo_data_full;
wire wr_fifo_mask_full;
wire wr_fifo_addr_almost_full;
wire wr_fifo_data_almost_full;
wire wr_fifo_mask_almost_full;
axi_fifo_ctrl u_axi_fifo_ctrl (
.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i),
.rw_req_i (rw_req_i ),
.rw_addr_i (rw_addr_i ),
.rd_len_i (rd_len_i ),
.wr_data_i (wr_data_i ),
.wr_mask_i (wr_mask_i ),
.rw_info_i (rw_info_i ),
.rw_ack_o (rw_ack_o ),
.rw_info_o (rw_info_o ),
.rd_data_o (rd_data_o ),
.rd_data_v_o (rd_data_v_o),
.rd_info_o (rd_info_o ),
.wr_fifo_almost_full_i(wr_fifo_addr_almost_full & wr_fifo_data_almost_full & wr_fifo_mask_almost_full),
.wr_fifo_full_i(wr_fifo_addr_full & wr_fifo_data_full & wr_fifo_mask_full),
.wr_fifo_we_o(wr_fifo_we),
.wr_fifo_addr_o(wr_fifo_addr_din),
.wr_fifo_data_o(wr_fifo_data_din),
.wr_fifo_mask_o(wr_fifo_mask_din),
.rd_fifo_almost_full_i(rd_fifo_addr_almost_full & rd_fifo_len_almost_full & rd_fifo_info_almost_full),
.rd_fifo_full_i(rd_fifo_addr_full & rd_fifo_len_full & rd_fifo_info_full),
.rd_fifo_addr_o(rd_fifo_addr_din),
.rd_fifo_len_o(rd_fifo_len_din),
.rd_fifo_info_o(rd_fifo_info_din),
.rd_fifo_we_o(rd_fifo_we),
.rd_fifo_empty_i(rd_fifo_addr_empty & rd_fifo_len_empty & rd_fifo_info_empty),
.rd_fifo_re_o(rd_fifo_data_re),
.rd_fifo_data_i(rd_fifo_data_dout),
.rd_fifo_data_v_i(rd_fifo_data_dout_v),
.rd_fifo_info_i(rd_fifo_info_dout),
.rw_fifo_busy_o(rw_fifo_busy_o)
);
// Instance of axi_m_rd
axi_m_rd u_axi_m_rd (
.ui_clk_i(sys_clk_i),
.ui_rst_i(sys_rst_i),
// Connect m_axi to s_axi
.m_axi_arid_o(s_axi_arid),
.m_axi_araddr_o(s_axi_araddr),
.m_axi_arlen_o(s_axi_arlen),
.m_axi_arsize_o(s_axi_arsize),
.m_axi_arburst_o(s_axi_arburst),
.m_axi_arlock_o(s_axi_arlock),
.m_axi_arcache_o(s_axi_arcache),
.m_axi_arprot_o(s_axi_arprot),
.m_axi_arvalid_o(s_axi_arvalid),
.m_axi_arready_i(s_axi_arready),
.m_axi_rready_o(s_axi_rready),
.m_axi_rid_i(s_axi_rid),
.m_axi_rdata_i(s_axi_rdata),
.m_axi_rresp_i(s_axi_rresp),
.m_axi_rlast_i(s_axi_rlast),
.m_axi_rvalid_i(s_axi_rvalid),
// Remaining ports
.rd_fifo_empty_i(rd_fifo_addr_empty & rd_fifo_len_empty),
.rd_fifo_re_o(rd_fifo_re),
.rd_fifo_addr_i(rd_fifo_addr_dout),
.rd_fifo_len_i(rd_fifo_len_dout),
.rd_fifo_almost_full_i(rd_fifo_data_almost_full),
.rd_fifo_we_o(rd_fifo_data_we),
.rd_fifo_din_o(rd_fifo_data_din)
);
fifo_ddr_addr fifo_rd_addr_inst(
.rst(sys_rst_i),
.wr_clk(sys_clk_i),
.wr_en(rd_fifo_we),
.din(rd_fifo_addr_din),
.full(rd_fifo_addr_full),
.almost_full(rd_fifo_addr_almost_full),
.rd_clk(sys_clk_i),
.rd_en(rd_fifo_re),
.dout(rd_fifo_addr_dout),
.empty(rd_fifo_addr_empty)
);
fifo_ddr_len fifo_rd_len_inst(
.rst(sys_rst_i),
.wr_clk(sys_clk_i),
.wr_en(rd_fifo_we),
.din(rd_fifo_len_din),
.full(rd_fifo_len_full),
.almost_full(rd_fifo_len_almost_full),
.rd_clk(sys_clk_i),
.rd_en(rd_fifo_re),
.dout(rd_fifo_len_dout),
.empty(rd_fifo_len_empty)
);
fifo_ddr_data fifo_rd_data_inst(
.rst(sys_rst_i),
.wr_clk(sys_clk_i),
.wr_en(rd_fifo_data_we),
.din(rd_fifo_data_din),
.almost_full(rd_fifo_data_almost_full),
.full(rd_fifo_data_full),
.prog_full(rd_fifo_data_prog_full),
.rd_clk(sys_clk_i),
.rd_en(rd_fifo_data_re),
.dout(rd_fifo_data_dout),
.empty(rd_fifo_data_empty),
.valid(rd_fifo_data_dout_v)
);
fifo_ddr_info fifo_rd_info_inst(
.srst(sys_rst_i),
.clk(sys_clk_i),
.wr_en(rd_fifo_we),
.din(rd_fifo_info_din),
.full(rd_fifo_info_full),
.almost_full(rd_fifo_info_almost_full),
.rd_en(rd_fifo_re),
.dout(rd_fifo_info_dout),
.empty(rd_fifo_info_empty)
);
// Instance of axi_m_wr
axi_m_wr u_axi_m_wr (
.ui_clk_i(sys_clk_i),
.ui_rst_i(sys_rst_i),
// Connect m_axi to s_axi
.m_axi_awid_o(s_axi_awid),
.m_axi_awaddr_o(s_axi_awaddr),
.m_axi_awlen_o(s_axi_awlen),
.m_axi_awsize_o(s_axi_awsize),
.m_axi_awburst_o(s_axi_awburst),
.m_axi_awlock_o(s_axi_awlock),
.m_axi_awcache_o(s_axi_awcache),
.m_axi_awprot_o(s_axi_awprot),
.m_axi_awvalid_o(s_axi_awvalid),
.m_axi_awready_i(s_axi_awready),
.m_axi_wdata_o(s_axi_wdata),
.m_axi_wstrb_o(s_axi_wstrb),
.m_axi_wlast_o(s_axi_wlast),
.m_axi_wvalid_o(s_axi_wvalid),
.m_axi_wready_i(s_axi_wready),
.m_axi_bready_o(s_axi_bready),
.m_axi_bid_i(s_axi_bid),
.m_axi_bresp_i(s_axi_bresp),
.m_axi_bvalid_i(s_axi_bvalid),
// Remaining ports
.wr_fifo_empty_i(wr_fifo_addr_empty && wr_fifo_data_empty && wr_fifo_mask_empty),
.wr_fifo_re_o(wr_fifo_re),
.wr_fifo_addr_i(wr_fifo_addr_dout),
.wr_fifo_len_i(1'b1),
.wr_fifo_data_i(wr_fifo_data_dout),
.wr_fifo_mask_i(wr_fifo_mask_dout)
);
fifo_ddr_addr fifo_wr_addr_inst(
.rst(sys_rst_i),
.wr_clk(sys_clk_i),
.wr_en(wr_fifo_we),
.din(wr_fifo_addr_din),
.full(wr_fifo_addr_full),
.almost_full(wr_fifo_addr_almost_full),
.rd_clk(sys_clk_i),
.rd_en(wr_fifo_re),
.dout(wr_fifo_addr_dout),
.empty(wr_fifo_addr_empty)
);
fifo_ddr_data fifo_wr_data_inst(
.rst(sys_rst_i),
.wr_clk(sys_clk_i),
.wr_en(wr_fifo_we),
.din(wr_fifo_data_din),
.full(wr_fifo_data_full),
.almost_full(wr_fifo_data_almost_full),
.rd_clk(sys_clk_i),
.rd_en(wr_fifo_re),
.dout(wr_fifo_data_dout),
.empty(wr_fifo_data_empty)
);
fifo_ddr_mask fifo_wr_mask_inst(
.rst(sys_rst_i),
.wr_clk(sys_clk_i),
.wr_en(wr_fifo_we),
.din(wr_fifo_mask_din),
.full(wr_fifo_mask_full),
.almost_full(wr_fifo_mask_almost_full),
.rd_clk(sys_clk_i),
.rd_en(wr_fifo_re),
.dout(wr_fifo_mask_dout),
.empty(wr_fifo_mask_empty)
);
endmodule