fix whole structure
This commit is contained in:
@@ -3,7 +3,7 @@
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<!-- -->
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="44" Path="D:/Project/Vivado/AX7325/ddr3_general_design/ddr_general_design.xpr">
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<Project Version="7" Minor="44" Path="D:/project/Vivado/project/AX7325/ddr_general_design/ddr_general_design.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="f70ee986e274458592343b96a4e9c625"/>
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@@ -36,13 +36,13 @@
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<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="7"/>
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<Option Name="WTModelSimExportSim" Val="7"/>
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<Option Name="WTQuestaExportSim" Val="7"/>
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<Option Name="WTIesExportSim" Val="7"/>
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<Option Name="WTVcsExportSim" Val="7"/>
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<Option Name="WTRivieraExportSim" Val="7"/>
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<Option Name="WTActivehdlExportSim" Val="7"/>
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<Option Name="WTXSimExportSim" Val="9"/>
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<Option Name="WTModelSimExportSim" Val="9"/>
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<Option Name="WTQuestaExportSim" Val="9"/>
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<Option Name="WTIesExportSim" Val="9"/>
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<Option Name="WTVcsExportSim" Val="9"/>
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<Option Name="WTRivieraExportSim" Val="9"/>
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<Option Name="WTActivehdlExportSim" Val="9"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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@@ -84,20 +84,6 @@
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<Attr Name="ScopedToCell" Val="pcie_ddr_mig_7series_0_0"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/ddr_ctrl.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/ip/ddr3_mig/mig_a.prj">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="ScopedToCell" Val="ddr3_mig"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/ddr_axi_wr.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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@@ -122,6 +108,46 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/fifo2axi_convert.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/fifo_axi_ctrl.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/axi2fifo_convert.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/ip/ddr_ctrl/ddr_ctrl.xci">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/ddr_ctrl_top.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="pcie_ddr_wrapper"/>
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@@ -153,8 +179,8 @@
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="ddr3_mig" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ddr3_mig">
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<File Path="$PSRCDIR/sources_1/ip/ddr3_mig/ddr3_mig.xci">
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<FileSet Name="fifo_ddr_info" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_ddr_info">
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<File Path="$PSRCDIR/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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@@ -163,12 +189,12 @@
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="ddr3_mig"/>
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<Option Name="TopModule" Val="fifo_ddr_info"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="fifo_ddr_wdara" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_ddr_wdara">
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<File Path="$PSRCDIR/sources_1/ip/fifo_ddr_wdara/fifo_ddr_wdara.xci">
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<FileSet Name="fifo_ddr_data" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_ddr_data">
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<File Path="$PSRCDIR/sources_1/ip/fifo_ddr_data/fifo_ddr_data.xci">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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@@ -177,21 +203,7 @@
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="fifo_ddr_wdara"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="fifo_ddr_rdata" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_ddr_rdata">
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<File Path="$PSRCDIR/sources_1/ip/fifo_ddr_rdata/fifo_ddr_rdata.xci">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="fifo_ddr_rdata"/>
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<Option Name="TopModule" Val="fifo_ddr_data"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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@@ -224,17 +236,7 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="ddr3_mig_synth_1" Type="Ft3:Synth" SrcSet="ddr3_mig" Part="xc7k325tffg900-2" ConstrsSet="ddr3_mig" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ddr3_mig_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="fifo_ddr_wdara_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_wdara" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_wdara" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_wdara_synth_1" IncludeInArchive="true">
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<Run Id="fifo_ddr_info_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_info" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_info" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_info_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
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<Desc>Vivado Synthesis Defaults</Desc>
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@@ -246,7 +248,7 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="fifo_ddr_rdata_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_rdata" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_rdata" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_rdata_synth_1" IncludeInArchive="true">
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<Run Id="fifo_ddr_data_synth_1" Type="Ft3:Synth" SrcSet="fifo_ddr_data" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_data" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_ddr_data_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
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<Desc>Vivado Synthesis Defaults</Desc>
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@@ -275,24 +277,7 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="ddr3_mig_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="ddr3_mig" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ddr3_mig_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="fifo_ddr_wdara_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_wdara" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_wdara_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Run Id="fifo_ddr_info_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_info" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_info_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
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<Desc>Default settings for Implementation.</Desc>
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@@ -311,7 +296,7 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="fifo_ddr_rdata_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_rdata" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_rdata_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Run Id="fifo_ddr_data_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_ddr_data" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_ddr_data_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
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<Desc>Default settings for Implementation.</Desc>
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