diff --git a/ddr_general_design.srcs/sources_1/ip/ddr3_mig/ddr3_mig.xci b/ddr_general_design.srcs/sources_1/ip/ddr_ctrl/ddr_ctrl.xci similarity index 93% rename from ddr_general_design.srcs/sources_1/ip/ddr3_mig/ddr3_mig.xci rename to ddr_general_design.srcs/sources_1/ip/ddr_ctrl/ddr_ctrl.xci index 13a5653..dd527f1 100644 --- a/ddr_general_design.srcs/sources_1/ip/ddr3_mig/ddr3_mig.xci +++ b/ddr_general_design.srcs/sources_1/ip/ddr_ctrl/ddr_ctrl.xci @@ -6,7 +6,7 @@ 1.0 - ddr3_mig + ddr_ctrl 0 @@ -1092,34 +1092,34 @@ 100000000 0 0.000 - 33 + 1 0 0 0 - 512 - 1 - 1 - 1 - 1 - 1 - 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 0 - 1 - 1 - 4 + 0 + 0 + 0 0 - 256 - 2 + 1 + 1 1 - 2 + 1 1 0.000 - AXI4 + AXI4LITE READ_WRITE 0 0 - 1 + 0 0 0 1 @@ -2169,14 +2169,14 @@ FALSE 0 0 - 33 + 32 32 32 4 1048576 - 512 + 32 4 - 8589934592 + 1048576 8 3 1 @@ -2196,24 +2196,24 @@ 1 2 1 - 30 + 8 3 - 2 - 2 - 2 - 64 + 1 + 1 + 1 + 8 OFF - 8 - 3 - 8 - 64 - 2 + 1 + 1 + 1 + 8 + 1 OFF - 16 + 14 1 1 1 - 4 + 2 1 8 8 @@ -2221,7 +2221,7 @@ OFF 1 OFF - 100000000 + 100.0 FALSE 8 3 @@ -2252,8 +2252,8 @@ 10 FALSE 10 - 800 - 1 + 1200.0 + 0 0.000 ACTIVE_LOW 29 @@ -2262,7 +2262,7 @@ 18 OFF 1 - NONE + DIFF 29 2 1 @@ -2295,15 +2295,15 @@ 18 1 1 - NOBUF + DIFF INTERNAL FALSE - 1 + 0 Custom - ddr3_mig + ddr_ctrl Custom Custom - mig_a.prj + kintex7 @@ -2329,141 +2329,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -2478,7 +2343,6 @@ - @@ -2497,7 +2361,6 @@ - @@ -2515,7 +2378,6 @@ - @@ -2534,7 +2396,6 @@ - @@ -2552,7 +2413,6 @@ - @@ -2571,7 +2431,6 @@ - @@ -2589,7 +2448,6 @@ - @@ -2608,7 +2466,6 @@ - @@ -2626,7 +2483,6 @@ - @@ -2645,7 +2501,6 @@ - @@ -2663,7 +2518,6 @@ - @@ -2682,7 +2536,6 @@ - @@ -2700,7 +2553,6 @@ - @@ -2719,7 +2571,6 @@ - @@ -2737,7 +2588,6 @@ - @@ -2756,20 +2606,24 @@ - - - + + + + + + - - + + + @@ -2787,14 +2641,9 @@ - - - - - diff --git a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_wdara/fifo_ddr_wdara.xci b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_data/fifo_ddr_data.xci similarity index 95% rename from ddr_general_design.srcs/sources_1/ip/fifo_ddr_wdara/fifo_ddr_wdara.xci rename to ddr_general_design.srcs/sources_1/ip/fifo_ddr_data/fifo_ddr_data.xci index 32c195b..4dcf84b 100644 --- a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_wdara/fifo_ddr_wdara.xci +++ b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_data/fifo_ddr_data.xci @@ -6,7 +6,7 @@ 1.0 - fifo_ddr_wdara + fifo_ddr_data @@ -152,9 +152,9 @@ 1 1 0 - 10 + 6 BlankString - 18 + 512 1 32 64 @@ -162,7 +162,7 @@ 64 2 0 - 18 + 512 0 1 0 @@ -217,8 +217,8 @@ 0 1 0 - 0 - 0 + 1 + 1 0 0 0 @@ -238,7 +238,7 @@ 0 1 0 - 1kx18 + 512x72 1kx18 512x36 1kx36 @@ -260,14 +260,14 @@ 0 0 0 - 1022 + 62 1023 1023 1023 1023 1023 1023 - 1021 + 61 0 0 0 @@ -277,10 +277,10 @@ 0 0 0 - 10 - 1024 + 6 + 64 1 - 10 + 6 0 0 0 @@ -310,8 +310,8 @@ 0 0 0 - 10 - 1024 + 6 + 64 1024 16 1024 @@ -319,7 +319,7 @@ 1024 16 1 - 10 + 6 10 4 10 @@ -337,10 +337,10 @@ 0 Slave_Interface_Clock_Enable Common_Clock - fifo_ddr_wdara + fifo_ddr_data 64 false - 10 + 6 false false 0 @@ -386,14 +386,14 @@ Common_Clock_Block_RAM Common_Clock_Block_RAM 0 - 1022 + 62 1023 1023 1023 1023 1023 1023 - 1021 + 61 false false false @@ -413,8 +413,8 @@ false false false - 18 - 1024 + 512 + 64 1024 16 1024 @@ -422,8 +422,8 @@ 1024 16 false - 18 - 1024 + 512 + 64 Embedded_Reg false false @@ -449,7 +449,7 @@ 0 1 false - 10 + 6 Fully_Registered Fully_Registered Fully_Registered @@ -473,14 +473,14 @@ false false false - false + true Active_High 0 - false + true Active_High 1 false - 10 + 6 false FIFO false @@ -548,6 +548,17 @@ + + + + + + + + + + + diff --git a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_rdata/fifo_ddr_rdata.xci b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci similarity index 99% rename from ddr_general_design.srcs/sources_1/ip/fifo_ddr_rdata/fifo_ddr_rdata.xci rename to ddr_general_design.srcs/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci index eb2af76..386584d 100644 --- a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_rdata/fifo_ddr_rdata.xci +++ b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci @@ -6,7 +6,7 @@ 1.0 - fifo_ddr_rdata + fifo_ddr_info @@ -217,8 +217,8 @@ 0 1 0 - 0 - 0 + 1 + 1 0 0 0 @@ -337,7 +337,7 @@ 0 Slave_Interface_Clock_Enable Common_Clock - fifo_ddr_rdata + fifo_ddr_info 64 false 10 @@ -473,10 +473,10 @@ false false false - false + true Active_High 0 - false + true Active_High 1 false @@ -548,6 +548,8 @@ + + diff --git a/ddr_general_design.srcs/sources_1/new/axi2fifo_convert.v b/ddr_general_design.srcs/sources_1/new/axi2fifo_convert.v new file mode 100644 index 0000000..f4c0933 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/new/axi2fifo_convert.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/03/19 10:32:12 +// Design Name: +// Module Name: axi2fifo_convert +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module axi2fifo_convert( + + ); +endmodule diff --git a/ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v b/ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v index b42c893..01a6df2 100644 --- a/ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v +++ b/ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v @@ -21,36 +21,36 @@ module ddr_axi_rd( - input ARESETN, //axi复位 - input ACLK, //axi时钟 + input aresetn, //axi复位 + input aclk, //axi时钟 //axi读通道写地址 - output [3:0] M_AXI_ARID , //读地址ID，用来标志一组写信号 - output [31:0] M_AXI_ARADDR , //读地址，给出一次写突发传输的读地址 - output [7:0] M_AXI_ARLEN , //突发长度，给出突发传输的次数 - output [2:0] M_AXI_ARSIZE , //突发大小，给出每次突发传输的字节数 - output [1:0] M_AXI_ARBURST, //突发类型 - output [1:0] M_AXI_ARLOCK , //总线锁信号，可提供操作的原子性 - output [3:0] M_AXI_ARCACHE, //内存类型，表明一次传输是怎样通过系统的 - output [2:0] M_AXI_ARPROT , //保护类型，表明一次传输的特权级及安全等级 - output [3:0] M_AXI_ARQOS , //质量服务QOS - output M_AXI_ARVALID, //有效信号，表明此通道的地址控制信号有效 - input M_AXI_ARREADY, //表明“从”可以接收地址和对应的控制信号 + output [3:0] m_axi_arid , //读地址ID，用来标志一组写信号 + output [31:0] m_axi_araddr , //读地址，给出一次写突发传输的读地址 + output [7:0] m_axi_arlen , //突发长度，给出突发传输的次数 + output [2:0] m_axi_arsize , //突发大小，给出每次突发传输的字节数 + output [1:0] m_axi_arburst, //突发类型 + output [1:0] m_axi_arlock , //总线锁信号，可提供操作的原子性 + output [3:0] m_axi_arcache, //内存类型，表明一次传输是怎样通过系统的 + output [2:0] m_axi_arprot , //保护类型，表明一次传输的特权级及安全等级 + output [3:0] m_axi_arqos , //质量服务QOS + output m_axi_arvalid, //有效信号，表明此通道的地址控制信号有效 + input m_axi_arready, //表明“从”可以接收地址和对应的控制信号 //axi读通道读数据 - input [3:0] M_AXI_RID , //读ID tag - input [63:0] M_AXI_RDATA , //读数据 - input [1:0] M_AXI_RRESP , //读响应，表明读传输的状态 - input M_AXI_RLAST , //表明读突发的最后一次传输 - input M_AXI_RVALID, //表明此通道信号有效 - output M_AXI_RREADY, //表明主机能够接收读数据和响应信息 + input [3:0] m_axi_rid , //读ID tag + input [63:0] m_axi_rdata , //读数据 + input [1:0] m_axi_rresp , //读响应，表明读传输的状态 + input m_axi_rlast , //表明读突发的最后一次传输 + input m_axi_rvalid, //表明此通道信号有效 + output m_axi_rready, //表明主机能够接收读数据和响应信息 //用户端fifo接口 - input RD_START , //读突发触发信号 - input [31:0] RD_ADRS , //地址 - input [9:0] RD_LEN , //长度 - output RD_READY , //读空闲 - output RD_FIFO_WE , //连接到读fifo的写使能 - output [63:0] RD_FIFO_DATA, //连接到读fifo的写数据 - output RD_DONE //完成一次突发 + input rd_start , //读突发触发信号 + input [31:0] rd_adrs , //地址 + input [9:0] rd_len , //长度 + output rd_ready , //读空闲 + output rd_fifo_we , //连接到读fifo的写使能 + output [63:0] rd_fifo_data, //连接到读fifo的写数据 + output rd_done //完成一次突发 ); //********************************************************************// @@ -74,25 +74,25 @@ reg reg_arvalid; //地址有效寄存器 //***************************** Main Code ****************************// //********************************************************************// -assign RD_DONE = (rd_state == S_RD_DONE) ; -assign M_AXI_ARID = 4'b1111;//地址id -assign M_AXI_ARADDR[31:0] = reg_rd_adrs[31:0];//地址 -assign M_AXI_ARLEN[7:0] = RD_LEN-32'd1;//突发长度 -assign M_AXI_ARSIZE[2:0] = 3'b011;//表示AXI总线每个数据宽度是8字节，64位 -assign M_AXI_ARBURST[1:0] = 2'b01;//地址递增方式传输 -assign M_AXI_ARLOCK = 1'b0; -assign M_AXI_ARCACHE[3:0] = 4'b0000; -assign M_AXI_ARPROT[2:0] = 3'b000; -assign M_AXI_ARQOS[3:0] = 4'b0000; -assign M_AXI_ARVALID = reg_arvalid; -assign M_AXI_RREADY = M_AXI_RVALID; -assign RD_READY = (rd_state == S_RD_IDLE)?1'b1:1'b0;//读空闲 -assign RD_FIFO_WE = M_AXI_RVALID;//读fifo的写使能信号 -assign RD_FIFO_DATA[63:0] = M_AXI_RDATA[63:0];//读fifo的写数据信号 +assign rd_done = (rd_state == S_RD_DONE) ; +assign m_axi_arid = 4'b1111;//地址id +assign m_axi_araddr[31:0] = reg_rd_adrs[31:0];//地址 +assign m_axi_arlen[7:0] = rd_len-32'd1;//突发长度 +assign m_axi_arsize[2:0] = 3'b011;//表示AXI总线每个数据宽度是8字节，64位 +assign m_axi_arburst[1:0] = 2'b01;//地址递增方式传输 +assign m_axi_arlock = 1'b0; +assign m_axi_arcache[3:0] = 4'b0000; +assign m_axi_arprot[2:0] = 3'b000; +assign m_axi_arqos[3:0] = 4'b0000; +assign m_axi_arvalid = reg_arvalid; +assign m_axi_rready = m_axi_rvalid; +assign rd_ready = (rd_state == S_RD_IDLE)?1'b1:1'b0;//读空闲 +assign rd_fifo_we = m_axi_rvalid;//读fifo的写使能信号 +assign rd_fifo_data[63:0] = m_axi_rdata[63:0];//读fifo的写数据信号 // 读状态机 - always @(posedge ACLK or negedge ARESETN) begin - if(!ARESETN) begin + always @(posedge aclk or negedge aresetn) begin + if(!aresetn) begin rd_state <= S_RD_IDLE; reg_rd_adrs[31:0] <= 32'd0; reg_rd_len[31:0] <= 32'd0; @@ -100,10 +100,10 @@ assign RD_FIFO_DATA[63:0] = M_AXI_RDATA[63:0];//读fifo的写数据信号 end else begin case(rd_state) S_RD_IDLE: begin//读空闲 - if(RD_START) begin//突发触发信号 + if(rd_start) begin//突发触发信号 rd_state <= S_RA_WAIT; - reg_rd_adrs[31:0] <= RD_ADRS[31:0]; - reg_rd_len[31:0] <= RD_LEN[9:0] -32'd1; + reg_rd_adrs[31:0] <= rd_adrs[31:0]; + reg_rd_len[31:0] <= rd_len[9:0] -32'd1; end reg_arvalid <= 1'b0; end @@ -115,14 +115,14 @@ assign RD_FIFO_DATA[63:0] = M_AXI_RDATA[63:0];//读fifo的写数据信号 reg_arvalid <= 1'b1;//拉高地址有效 end S_RD_WAIT: begin //读取数据等待 - if(M_AXI_ARREADY) begin + if(m_axi_arready) begin rd_state <= S_RD_PROC; reg_arvalid <= 1'b0;//握手成功就拉低 end end S_RD_PROC: begin //接受循环 - if(M_AXI_RVALID) begin //收到数据有效，握手成功 - if(M_AXI_RLAST) begin //收到最后一个数据 + if(m_axi_rvalid) begin //收到数据有效，握手成功 + if(m_axi_rlast) begin //收到最后一个数据 rd_state<= S_RD_DONE; end end diff --git a/ddr_general_design.srcs/sources_1/new/ddr_axi_wr.v b/ddr_general_design.srcs/sources_1/new/ddr_axi_wr.v index 90bddf0..d9da7fa 100644 --- a/ddr_general_design.srcs/sources_1/new/ddr_axi_wr.v +++ b/ddr_general_design.srcs/sources_1/new/ddr_axi_wr.v @@ -21,39 +21,39 @@ module ddr_axi_wr( - input ARESETN , //axi复位 - input ACLK , //axi总时钟 + input aresetn , //axi复位 + input aclk , //axi总时钟 //axi4写通道地址通道 - output [3:0] M_AXI_AWID , //写地址ID，用来标志一组写信号 - output [31:0] M_AXI_AWADDR , //写地址，给出一次写突发传输的写地址 - output [7:0] M_AXI_AWLEN , //突发长度，给出突发传输的次数 - output [2:0] M_AXI_AWSIZE , //突发大小，给出每次突发传输的字节数 - output [1:0] M_AXI_AWBURST, //突发类型 - output M_AXI_AWLOCK , //总线锁信号，可提供操作的原子性 - output [3:0] M_AXI_AWCACHE, //内存类型，表明一次传输是怎样通过系统的 - output [2:0] M_AXI_AWPROT , //保护类型，表明一次传输的特权级及安全等级 - output [3:0] M_AXI_AWQOS , //质量服务QoS - output M_AXI_AWVALID, //有效信号，表明此通道的地址控制信号有效 - input M_AXI_AWREADY, //表明“从”可以接收地址和对应的控制信号 + output [3:0] m_axi_awid , //写地址ID，用来标志一组写信号 + output [31:0] m_axi_awaddr , //写地址，给出一次写突发传输的写地址 + output [7:0] m_axi_awlen , //突发长度，给出突发传输的次数 + output [2:0] m_axi_awsize , //突发大小，给出每次突发传输的字节数 + output [1:0] m_axi_awburst, //突发类型 + output m_axi_awlock , //总线锁信号，可提供操作的原子性 + output [3:0] m_axi_awcache, //内存类型，表明一次传输是怎样通过系统的 + output [2:0] m_axi_awprot , //保护类型，表明一次传输的特权级及安全等级 + output [3:0] m_axi_awqos , //质量服务QoS + output m_axi_awvalid, //有效信号，表明此通道的地址控制信号有效 + input m_axi_awready, //表明“从”可以接收地址和对应的控制信号 //axi4写通道数据通道 - output [63:0] M_AXI_WDATA , //写数据 - output [7:0] M_AXI_WSTRB , //写数据有效的字节线 - output M_AXI_WLAST , //表明此次传输是最后一个突发传输 - output M_AXI_WVALID , //写有效，表明此次写有效 - input M_AXI_WREADY , //表明从机可以接收写数据 + output [63:0] m_axi_wdata , //写数据 + output [7:0] m_axi_wstrb , //写数据有效的字节线 + output m_axi_wlast , //表明此次传输是最后一个突发传输 + output m_axi_wvalid , //写有效，表明此次写有效 + input m_axi_wready , //表明从机可以接收写数据 //axi4写通道应答通道 - input [3:0] M_AXI_BID , //写响应ID TAG - input [1:0] M_AXI_BRESP , //写响应，表明写传输的状态 - input M_AXI_BVALID , //写响应有效 - output M_AXI_BREADY , //表明主机能够接收写响应 + input [3:0] m_axi_bid , //写响应ID TAG + input [1:0] m_axi_bresp , //写响应，表明写传输的状态 + input m_axi_bvalid , //写响应有效 + output m_axi_bready , //表明主机能够接收写响应 //用户端信号 - input WR_START , //写突发触发信号 - input [31:0] WR_ADRS , //地址 - input [9:0] WR_LEN , //长度 - output WR_READY , //写空闲 - output WR_FIFO_RE , //连接到写fifo的读使能 - input [63:0] WR_FIFO_DATA , //连接到fifo的读数据 - output WR_DONE //完成一次突发 + input wr_start , //写突发触发信号 + input [31:0] wr_adrs , //地址 + input [9:0] wr_len , //长度 + output wr_ready , //写空闲 + output wr_fifo_re , //连接到写fifo的读使能 + input [63:0] wr_fifo_data , //连接到fifo的读数据 + output wr_done //完成一次突发 ); //********************************************************************// @@ -80,40 +80,40 @@ reg [7:0] reg_w_len ; //突发长度最大256，实测128最佳 //********************************************************************// //写完成信号的写状态完成 -assign WR_DONE = (wr_state == S_WR_DONE); +assign wr_done = (wr_state == S_WR_DONE); //写fifo的读使能为axi数据握手成功 -assign WR_FIFO_RE = ((reg_wvalid & M_AXI_WREADY )); +assign wr_fifo_re = ((reg_wvalid & m_axi_wready )); //只有一个主机，可随意设置 -assign M_AXI_AWID = 4'b1111; +assign m_axi_awid = 4'b1111; //把地址赋予总线 -assign M_AXI_AWADDR[31:0] = reg_wr_adrs[31:0]; +assign m_axi_awaddr[31:0] = reg_wr_adrs[31:0]; //一次突发传输1长度 -assign M_AXI_AWLEN[7:0] = WR_LEN-'d1; +assign m_axi_awlen[7:0] = wr_len-'d1; //表示AXI总线每个数据宽度是8字节，64位 -assign M_AXI_AWSIZE[2:0] = 3'b011; +assign m_axi_awsize[2:0] = 3'b011; //01代表地址递增，10代表递减 -assign M_AXI_AWBURST[1:0] = 2'b01; -assign M_AXI_AWLOCK = 1'b0; -assign M_AXI_AWCACHE[3:0] = 4'b0000; -assign M_AXI_AWPROT[2:0] = 3'b000; -assign M_AXI_AWQOS[3:0] = 4'b0000; +assign m_axi_awburst[1:0] = 2'b01; +assign m_axi_awlock = 1'b0; +assign m_axi_awcache[3:0] = 4'b0000; +assign m_axi_awprot[2:0] = 3'b000; +assign m_axi_awqos[3:0] = 4'b0000; //地址握手信号AWVALID -assign M_AXI_AWVALID = reg_awvalid; +assign m_axi_awvalid = reg_awvalid; //fifo数据赋予总线 -assign M_AXI_WDATA[63:0] = WR_FIFO_DATA[63:0]; -assign M_AXI_WSTRB[7:0] = 8'hFF; +assign m_axi_wdata[63:0] = wr_fifo_data[63:0]; +assign m_axi_wstrb[7:0] = 8'hFF; //写到最后一个数据 -assign M_AXI_WLAST =(reg_w_len[7:0] == 8'd0)?'b1:'b0; +assign m_axi_wlast =(reg_w_len[7:0] == 8'd0)?'b1:'b0; //数据握手信号WVALID -assign M_AXI_WVALID = reg_wvalid; +assign m_axi_wvalid = reg_wvalid; //这个信号是告诉AXI我收到你的应答 -assign M_AXI_BREADY = M_AXI_BVALID; +assign m_axi_bready = m_axi_bvalid; //axi状态机空闲信号 -assign WR_READY = (wr_state == S_WR_IDLE)?1'b1:1'b0; +assign wr_ready = (wr_state == S_WR_IDLE)?1'b1:1'b0; //axi写过程状态机 - always @(posedge ACLK or negedge ARESETN) begin - if(!ARESETN) begin + always @(posedge aclk or negedge aresetn) begin + if(!aresetn) begin wr_state <= S_WR_IDLE; reg_wr_adrs[31:0] <= 32'd0; reg_awvalid <= 1'b0; @@ -124,9 +124,9 @@ assign WR_READY = (wr_state == S_WR_IDLE)?1'b1:1'b0; end else begin case(wr_state) S_WR_IDLE: begin //写空闲 - if(WR_START) begin //触发写过程 + if(wr_start) begin //触发写过程 wr_state <= S_WA_WAIT; - reg_wr_adrs[31:0] <= WR_ADRS[31:0]; + reg_wr_adrs[31:0] <= wr_adrs[31:0]; end reg_awvalid <= 1'b0; reg_wvalid <= 1'b0; @@ -141,14 +141,14 @@ assign WR_READY = (wr_state == S_WR_IDLE)?1'b1:1'b0; reg_wvalid <= 1'b1;//拉高数据有效信号 end S_WD_WAIT: begin - if(M_AXI_AWREADY) begin//等待写地址就绪 + if(m_axi_awready) begin//等待写地址就绪 wr_state <= S_WD_PROC; - reg_w_len<=WR_LEN-'d1;//127代表128个长度，0代表1个长度 + reg_w_len<=wr_len-'d1;//127代表128个长度，0代表1个长度 reg_awvalid <= 1'b0; end end S_WD_PROC: begin//等待AXI写数据就绪信号 - if(M_AXI_WREADY) begin//拉高了就可以输出fifo使能信号开始读 + if(m_axi_wready) begin//拉高了就可以输出fifo使能信号开始读 if(reg_w_len[7:0] == 8'd0) begin//完成数据写过程 wr_state <= S_WR_WAIT; @@ -165,7 +165,7 @@ assign WR_READY = (wr_state == S_WR_IDLE)?1'b1:1'b0; S_WR_WAIT: begin//等待写的AXI应答信号 reg_w_last<='b0; //M_AXI_BVALID拉高表示写成功，然后状态机完成一次突发传输 - if(M_AXI_BVALID) begin + if(m_axi_bvalid) begin wr_state <= S_WR_DONE; end end diff --git a/ddr_general_design.srcs/sources_1/new/ddr_ctrl.v b/ddr_general_design.srcs/sources_1/new/ddr_ctrl_top.v similarity index 51% rename from ddr_general_design.srcs/sources_1/new/ddr_ctrl.v rename to ddr_general_design.srcs/sources_1/new/ddr_ctrl_top.v index f6e75df..ffcfec2 100644 --- a/ddr_general_design.srcs/sources_1/new/ddr_ctrl.v +++ b/ddr_general_design.srcs/sources_1/new/ddr_ctrl_top.v @@ -20,7 +20,7 @@ ////////////////////////////////////////////////////////////////////////////////// -module ddr_ctrl( +module ddr_ctrl_top( // Inouts inout [63:0] ddr3_dq, inout [7:0] ddr3_dqs_n, @@ -39,13 +39,9 @@ module ddr_ctrl( output [7:0] ddr3_dm, output [1:0] ddr3_odt, // Inputs - // Single-ended system clock input sys_clk_i, output tg_compare_error, output init_calib_complete, - // System reset - Default polarity of sys_rst pin is Active Low. - // System reset polarity will change based on the option - // selected in GUI. input sys_rst ); @@ -69,151 +65,155 @@ module ddr_ctrl( // Range: 0, 1 - // Slave Interface Write Address Ports - wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid; - wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr; - wire [7:0] s_axi_awlen; - wire [2:0] s_axi_awsize; - wire [1:0] s_axi_awburst; - wire [0:0] s_axi_awlock; - wire [3:0] s_axi_awcache; - wire [2:0] s_axi_awprot; - wire s_axi_awvalid; - wire s_axi_awready; - // Slave Interface Write Data Ports - wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata; - wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb; - wire s_axi_wlast; - wire s_axi_wvalid; - wire s_axi_wready; - // Slave Interface Write Response Ports - wire s_axi_bready; - wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid; - wire [1:0] s_axi_bresp; - wire s_axi_bvalid; - // Slave Interface Read Address Ports - wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid; - wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr; - wire [7:0] s_axi_arlen; - wire [2:0] s_axi_arsize; - wire [1:0] s_axi_arburst; - wire [0:0] s_axi_arlock; - wire [3:0] s_axi_arcache; - wire [2:0] s_axi_arprot; - wire s_axi_arvalid; - wire s_axi_arready; - // Slave Interface Read Data Ports - wire s_axi_rready; - wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid; - wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata; - wire [1:0] s_axi_rresp; - wire s_axi_rlast; - wire s_axi_rvalid; +// Slave Interface Write Address Ports + wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid; + wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr; + wire [7:0] s_axi_awlen; + wire [2:0] s_axi_awsize; + wire [1:0] s_axi_awburst; + wire [0:0] s_axi_awlock; + wire [3:0] s_axi_awcache; + wire [2:0] s_axi_awprot; + wire s_axi_awvalid; + wire s_axi_awready; +// Slave Interface Write Data Ports + wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata; + wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb; + wire s_axi_wlast; + wire s_axi_wvalid; + wire s_axi_wready; +// Slave Interface Write Response Ports + wire s_axi_bready; + wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid; + wire [1:0] s_axi_bresp; + wire s_axi_bvalid; +// Slave Interface Read Address Ports + wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid; + wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr; + wire [7:0] s_axi_arlen; + wire [2:0] s_axi_arsize; + wire [1:0] s_axi_arburst; + wire [0:0] s_axi_arlock; + wire [3:0] s_axi_arcache; + wire [2:0] s_axi_arprot; + wire s_axi_arvalid; + wire s_axi_arready; +// Slave Interface Read Data Ports + wire s_axi_rready; + wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid; + wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata; + wire [1:0] s_axi_rresp; + wire s_axi_rlast; + wire s_axi_rvalid; + +fifo_axi_ctrl fifo_axi_ctrl_inst( + +); -// output declaration of module ddr_axi_rd -wire [3:0] M_AXI_ARID; -wire [31:0] M_AXI_ARADDR; -wire [7:0] M_AXI_ARLEN; -wire [2:0] M_AXI_ARSIZE; -wire [1:0] M_AXI_ARBURST; -wire [1:0] M_AXI_ARLOCK; -wire [3:0] M_AXI_ARCACHE; -wire [2:0] M_AXI_ARPROT; -wire [3:0] M_AXI_ARQOS; -wire M_AXI_ARVALID; -wire M_AXI_RREADY; -wire RD_READY; -wire RD_FIFO_WE; -wire [63:0] RD_FIFO_DATA; -wire RD_DONE; +// Output declaration of module ddr_axi_rd + wire [3:0] m_axi_arid; + wire [31:0] m_axi_araddr; + wire [7:0] m_axi_arlen; + wire [2:0] m_axi_arsize; + wire [1:0] m_axi_arburst; + wire [1:0] m_axi_arlock; + wire [3:0] m_axi_arcache; + wire [2:0] m_axi_arprot; + wire [3:0] m_axi_arqos; + wire m_axi_arvalid; + wire m_axi_rready; + wire rd_ready; + wire rd_fifo_we; + wire [63:0] rd_fifo_data; + wire rd_done; ddr_axi_rd u_ddr_axi_rd( - .ARESETN (ARESETN ), - .ACLK (ACLK ), - .M_AXI_ARID (M_AXI_ARID ), - .M_AXI_ARADDR (M_AXI_ARADDR ), - .M_AXI_ARLEN (M_AXI_ARLEN ), - .M_AXI_ARSIZE (M_AXI_ARSIZE ), - .M_AXI_ARBURST (M_AXI_ARBURST ), - .M_AXI_ARLOCK (M_AXI_ARLOCK ), - .M_AXI_ARCACHE (M_AXI_ARCACHE ), - .M_AXI_ARPROT (M_AXI_ARPROT ), - .M_AXI_ARQOS (M_AXI_ARQOS ), - .M_AXI_ARVALID (M_AXI_ARVALID ), - .M_AXI_ARREADY (M_AXI_ARREADY ), - .M_AXI_RID (M_AXI_RID ), - .M_AXI_RDATA (M_AXI_RDATA ), - .M_AXI_RRESP (M_AXI_RRESP ), - .M_AXI_RLAST (M_AXI_RLAST ), - .M_AXI_RVALID (M_AXI_RVALID ), - .M_AXI_RREADY (M_AXI_RREADY ), - .RD_START (RD_START ), - .RD_ADRS (RD_ADRS ), - .RD_LEN (RD_LEN ), - .RD_READY (RD_READY ), - .RD_FIFO_WE (RD_FIFO_WE ), - .RD_FIFO_DATA (RD_FIFO_DATA ), - .RD_DONE (RD_DONE ) + .aresetn (aresetn ), + .aclk (aclk ), + .m_axi_arid (m_axi_arid ), + .m_axi_araddr (m_axi_araddr ), + .m_axi_arlen (m_axi_arlen ), + .m_axi_arsize (m_axi_arsize ), + .m_axi_arburst (m_axi_arburst ), + .m_axi_arlock (m_axi_arlock ), + .m_axi_arcache (m_axi_arcache ), + .m_axi_arprot (m_axi_arprot ), + .m_axi_arqos (m_axi_arqos ), + .m_axi_arvalid (m_axi_arvalid ), + .m_axi_arready (m_axi_arready ), + .m_axi_rid (m_axi_rid ), + .m_axi_rdata (m_axi_rdata ), + .m_axi_rresp (m_axi_rresp ), + .m_axi_rlast (m_axi_rlast ), + .m_axi_rvalid (m_axi_rvalid ), + .m_axi_rready (m_axi_rready ), + .rd_start (rd_start ), + .rd_adrs (rd_adrs ), + .rd_len (rd_len ), + .rd_ready (rd_ready ), + .rd_fifo_we (rd_fifo_we ), + .rd_fifo_data (rd_fifo_data ), + .rd_done (rd_done ) ); -// output declaration of module ddr_axi_wr -wire [3:0] M_AXI_AWID; -wire [31:0] M_AXI_AWADDR; -wire [7:0] M_AXI_AWLEN; -wire [2:0] M_AXI_AWSIZE; -wire [1:0] M_AXI_AWBURST; -wire M_AXI_AWLOCK; -wire [3:0] M_AXI_AWCACHE; -wire [2:0] M_AXI_AWPROT; -wire [3:0] M_AXI_AWQOS; -wire M_AXI_AWVALID; -wire [63:0] M_AXI_WDATA; -wire [7:0] M_AXI_WSTRB; -wire M_AXI_WLAST; -wire M_AXI_WVALID; -wire M_AXI_BREADY; -wire WR_READY; -wire WR_FIFO_RE; -wire WR_DONE; +// Output declaration of module ddr_axi_wr + wire [3:0] m_axi_awid; + wire [31:0] m_axi_awaddr; + wire [7:0] m_axi_awlen; + wire [2:0] m_axi_awsize; + wire [1:0] m_axi_awburst; + wire m_axi_awlock; + wire [3:0] m_axi_awcache; + wire [2:0] m_axi_awprot; + wire [3:0] m_axi_awqos; + wire m_axi_awvalid; + wire [63:0] m_axi_wdata; + wire [7:0] m_axi_wstrb; + wire m_axi_wlast; + wire m_axi_wvalid; + wire m_axi_bready; + wire wr_ready; + wire wr_fifo_re; + wire wr_done; ddr_axi_wr u_ddr_axi_wr( - .ARESETN (ARESETN ), - .ACLK (ACLK ), - .M_AXI_AWID (M_AXI_AWID ), - .M_AXI_AWADDR (M_AXI_AWADDR ), - .M_AXI_AWLEN (M_AXI_AWLEN ), - .M_AXI_AWSIZE (M_AXI_AWSIZE ), - .M_AXI_AWBURST (M_AXI_AWBURST ), - .M_AXI_AWLOCK (M_AXI_AWLOCK ), - .M_AXI_AWCACHE (M_AXI_AWCACHE ), - .M_AXI_AWPROT (M_AXI_AWPROT ), - .M_AXI_AWQOS (M_AXI_AWQOS ), - .M_AXI_AWVALID (M_AXI_AWVALID ), - .M_AXI_AWREADY (M_AXI_AWREADY ), - .M_AXI_WDATA (M_AXI_WDATA ), - .M_AXI_WSTRB (M_AXI_WSTRB ), - .M_AXI_WLAST (M_AXI_WLAST ), - .M_AXI_WVALID (M_AXI_WVALID ), - .M_AXI_WREADY (M_AXI_WREADY ), - .M_AXI_BID (M_AXI_BID ), - .M_AXI_BRESP (M_AXI_BRESP ), - .M_AXI_BVALID (M_AXI_BVALID ), - .M_AXI_BREADY (M_AXI_BREADY ), - .WR_START (WR_START ), - .WR_ADRS (WR_ADRS ), - .WR_LEN (WR_LEN ), - .WR_READY (WR_READY ), - .WR_FIFO_RE (WR_FIFO_RE ), - .WR_FIFO_DATA (WR_FIFO_DATA ), - .WR_DONE (WR_DONE ) + .aresetn (aresetn ), + .aclk (aclk ), + .m_axi_awid (m_axi_awid ), + .m_axi_awaddr (m_axi_awaddr ), + .m_axi_awlen (m_axi_awlen ), + .m_axi_awsize (m_axi_awsize ), + .m_axi_awburst (m_axi_awburst ), + .m_axi_awlock (m_axi_awlock ), + .m_axi_awcache (m_axi_awcache ), + .m_axi_awprot (m_axi_awprot ), + .m_axi_awqos (m_axi_awqos ), + .m_axi_awvalid (m_axi_awvalid ), + .m_axi_awready (m_axi_awready ), + .m_axi_wdata (m_axi_wdata ), + .m_axi_wstrb (m_axi_wstrb ), + .m_axi_wlast (m_axi_wlast ), + .m_axi_wvalid (m_axi_wvalid ), + .m_axi_wready (m_axi_wready ), + .m_axi_bid (m_axi_bid ), + .m_axi_bresp (m_axi_bresp ), + .m_axi_bvalid (m_axi_bvalid ), + .m_axi_bready (m_axi_bready ), + .wr_start (wr_start ), + .wr_adrs (wr_adrs ), + .wr_len (wr_len ), + .wr_ready (wr_ready ), + .wr_fifo_re (wr_fifo_re ), + .wr_fifo_data (wr_fifo_data ), + .wr_done (wr_done ) ); - ddr3_mig u_ddr3_mig( +ddr_ctrl ddr_ctrl_inst( // Memory interface ports .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), @@ -259,7 +259,6 @@ ddr_axi_wr u_ddr_axi_wr( .s_axi_awvalid (s_axi_awvalid), .s_axi_awready (s_axi_awready), - // Slave Interface Write Data Ports .s_axi_wdata (s_axi_wdata), .s_axi_wstrb (s_axi_wstrb), @@ -267,14 +266,12 @@ ddr_axi_wr u_ddr_axi_wr( .s_axi_wvalid (s_axi_wvalid), .s_axi_wready (s_axi_wready), - // Slave Interface Write Response Ports .s_axi_bid (s_axi_bid), .s_axi_bresp (s_axi_bresp), .s_axi_bvalid (s_axi_bvalid), .s_axi_bready (s_axi_bready), - // Slave Interface Read Address Ports .s_axi_arid (s_axi_arid), .s_axi_araddr (s_axi_araddr), @@ -288,7 +285,6 @@ ddr_axi_wr u_ddr_axi_wr( .s_axi_arvalid (s_axi_arvalid), .s_axi_arready (s_axi_arready), - // Slave Interface Read Data Ports .s_axi_rid (s_axi_rid), .s_axi_rdata (s_axi_rdata), diff --git a/ddr_general_design.srcs/sources_1/new/fifo2axi_convert.v b/ddr_general_design.srcs/sources_1/new/fifo2axi_convert.v new file mode 100644 index 0000000..6f9cbd3 --- /dev/null +++ b/ddr_general_design.srcs/sources_1/new/fifo2axi_convert.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/03/19 10:25:21 +// Design Name: +// Module Name: fifo2axi_convert +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module fifo2axi_convert( + + ); +endmodule diff --git a/ddr_general_design.srcs/sources_1/new/fifo_axi_ctrl.v b/ddr_general_design.srcs/sources_1/new/fifo_axi_ctrl.v new file mode 100644 index 0000000..a99111d --- /dev/null +++ b/ddr_general_design.srcs/sources_1/new/fifo_axi_ctrl.v @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/03/19 10:26:57 +// Design Name: +// Module Name: fifo_axi_ctrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module fifo_axi_ctrl( + + ); + + + + fifo2axi_convert fifo2axi_convert_inst( + + ); + + axi2fifo_convert axi2fifo_convert_inst( + + ); + + + + fifo_ddr_addr fifo_ddr_raddr_inst( + + ); + + fifo_ddr_data fifo_ddr_rdata_inst( + + ); + + fifo_ddr_addr fifo_ddr_waddr_inst( + + ); + + fifo_ddr_data fifo_ddr_wdata_inst( + + ); + + fifo_ddr_info fifo_ddr_info_inst( + + ); +endmodule diff --git a/ddr_general_design.xpr b/ddr_general_design.xpr index 8794a46..718b5cf 100644 --- a/ddr_general_design.xpr +++ b/ddr_general_design.xpr @@ -3,7 +3,7 @@ - +