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v2.0_fifo_interface

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包焕垲
2025-04-27 19:07:35 +08:00
commit 66ef804e17
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ddr3_general_design.srcs/sources_1/new/ddr_axi_m_rd.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/27 16:50:57
// Design Name:
// Module Name: ddr_axi_m_rd
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr_axi_m_rd #(
parameter ADDR_WIDTH = 33, // 8GB
parameter DATA_WIDTH = 128 // lowest 3 bits should be 0
)
(
input ui_clk_i,
input ui_rst_i,
// Master Interface Read Address Ports
output [3:0] m_axi_arid_o,
output [ADDR_WIDTH-1:0] m_axi_araddr_o,
output [7:0] m_axi_arlen_o,
output [2:0] m_axi_arsize_o,
output [1:0] m_axi_arburst_o,
output [0:0] m_axi_arlock_o,
output [3:0] m_axi_arcache_o,
output [2:0] m_axi_arprot_o,
output m_axi_arvalid_o,
input m_axi_arready_i,
// Master Interface Read Data Ports
output m_axi_rready_o,
input [3:0] m_axi_rid_i,
input [DATA_WIDTH-1:0] m_axi_rdata_i,
input [1:0] m_axi_rresp_i,
input m_axi_rlast_i,
input m_axi_rvalid_i,
input fifo_ddr_rd_empty_i,
output fifo_ddr_rd_rd_en_o,
input fifo_ddr_rd_v_i,
input [ADDR_WIDTH-1:0] fifo_ddr_rd_addr_i,
input [7:0] fifo_ddr_rd_len_i,
input fifo_ddr_rdata_almost_full_i,
output fifo_ddr_rdata_wr_en_o,
output [DATA_WIDTH-1:0] fifo_ddr_rdata_o
);
localparam [2:0] RSIZE_VALUE = $clog2(DATA_WIDTH/8);
localparam [4:0]
S_RD_IDLE = 5'b00001,
S_RD_ADDR_START = 5'b00010,
S_RD_ADDR_WAIT = 5'b00100,
S_RD_DATA = 5'b01000,
S_RD_DONE = 5'b10000;
reg [ 4:0] c_state;
reg [ 4:0] n_state;
reg fifo_ddr_rd_rd_en;
reg [ADDR_WIDTH-1:0] fifo_ddr_rd_addr;
reg [ 7:0] fifo_ddr_rd_len;
reg fifo_ddr_rd_v;
reg m_axi_rready;
assign m_axi_arid_o = 4'b0;
assign m_axi_araddr_o = fifo_ddr_rd_addr;
assign m_axi_arlen_o = fifo_ddr_rd_len - 1'b1;
assign m_axi_arsize_o = RSIZE_VALUE;
assign m_axi_arburst_o = 2'b01; // INCR
assign m_axi_arlock_o = 1'b0;
assign m_axi_arcache_o = 4'b0000;
assign m_axi_arprot_o = 3'b000;
assign m_axi_arvalid_o = fifo_ddr_rd_v;
assign m_axi_rready_o = m_axi_rready;
assign fifo_ddr_rd_rd_en_o = fifo_ddr_rd_rd_en;
assign fifo_ddr_rdata_wr_en_o = m_axi_rvalid_i;
assign fifo_ddr_rdata_o = m_axi_rdata_i;
always @(posedge ui_clk_i or posedge ui_rst_i) begin
if (ui_rst_i) begin
c_state <= S_RD_IDLE;
end else begin
c_state <= n_state;
end
end
always @(*) begin
fifo_ddr_rd_rd_en = 1'b0;
fifo_ddr_rd_v = 1'b0;
n_state = S_RD_IDLE;
case(c_state)
S_RD_IDLE: begin
fifo_ddr_rd_addr = 33'b0;
fifo_ddr_rd_len = 8'b0;
if (!fifo_ddr_rd_empty_i) begin
fifo_ddr_rd_rd_en = 1'b1;
n_state = S_RD_ADDR_START;
end else begin
n_state = S_RD_IDLE;
end
end
S_RD_ADDR_START: begin
fifo_ddr_rd_addr = fifo_ddr_rd_addr_i;
fifo_ddr_rd_len = fifo_ddr_rd_len_i;
fifo_ddr_rd_v = 1'b1;
if(m_axi_arready_i) begin
n_state = S_RD_DATA;
end
else begin
n_state = S_RD_ADDR_WAIT;
end
end
S_RD_ADDR_WAIT: begin
fifo_ddr_rd_v = 1'b1;
if(m_axi_arready_i) begin
n_state = S_RD_DATA;
end
else begin
n_state = S_RD_ADDR_WAIT;
end
end
S_RD_DATA: begin
casex({m_axi_rvalid_i, m_axi_rlast_i, fifo_ddr_rdata_almost_full_i})
3'b0xx, 3'b100: begin
m_axi_rready = 1'b1;
n_state = S_RD_DATA;
end
3'b11x: begin
m_axi_rready = 1'b1;
n_state = S_RD_DONE;
end
3'b101: begin // overflow
m_axi_rready = 1'b0;
n_state = S_RD_DATA;
end
endcase
end
S_RD_DONE: begin
n_state = S_RD_IDLE;
end
default: begin
n_state = S_RD_IDLE;
end
endcase
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/04/02 14:35:06
// Design Name:
// Module Name: ddr_axi_m_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr_axi_m_top #(
parameter ADDR_WIDTH = 33, // 8GB
parameter DATA_WIDTH = 128 // lowest 3 bits should be 0
)
(
input sys_clk_i,
input sys_rst_i,
input ui_clk_i,
input ui_rst_i,
// Master Interface Read Address Ports
output [3:0] m_axi_arid_o,
output [ADDR_WIDTH-1:0] m_axi_araddr_o,
output [7:0] m_axi_arlen_o,
output [2:0] m_axi_arsize_o,
output [1:0] m_axi_arburst_o,
output [0:0] m_axi_arlock_o,
output [3:0] m_axi_arcache_o,
output [2:0] m_axi_arprot_o,
output m_axi_arvalid_o,
input m_axi_arready_i,
// Master Interface Read Data Ports
output m_axi_rready_o,
input [3:0] m_axi_rid_i,
input [DATA_WIDTH-1:0] m_axi_rdata_i,
input [1:0] m_axi_rresp_i,
input m_axi_rlast_i,
input m_axi_rvalid_i,
// Master Interface Write Address Ports
output [3:0] m_axi_awid_o,
output [ADDR_WIDTH-1:0] m_axi_awaddr_o,
output [7:0] m_axi_awlen_o,
output [2:0] m_axi_awsize_o,
output [1:0] m_axi_awburst_o,
output [0:0] m_axi_awlock_o,
output [3:0] m_axi_awcache_o,
output [2:0] m_axi_awprot_o,
output m_axi_awvalid_o,
input m_axi_awready_i,
// Master Interface Write Data Ports
output [DATA_WIDTH-1:0] m_axi_wdata_o,
output [DATA_WIDTH/8-1:0] m_axi_wstrb_o,
output m_axi_wlast_o,
output m_axi_wvalid_o,
input m_axi_wready_i,
// Master Interface Write Response Ports
output m_axi_bready_o,
input [3:0] m_axi_bid_i,
input [1:0] m_axi_bresp_i,
input m_axi_bvalid_i,
output fifo_ddr_rd_almost_full_o,
output fifo_ddr_rd_full_o,
input [ADDR_WIDTH-1:0] fifo_ddr_rd_addr_i,
input [7:0] fifo_ddr_rd_len_i,
input fifo_ddr_rd_wr_en_i,
output fifo_ddr_rdata_empty_o,
output [DATA_WIDTH-1:0] fifo_ddr_rdata_o,
output fifo_ddr_rdata_v_o,
input fifo_ddr_rdata_rd_en_i,
output fifo_ddr_wr_almost_full_o,
output fifo_ddr_wr_full_o,
input [ADDR_WIDTH-1:0] fifo_ddr_wr_addr_i,
input [7:0] fifo_ddr_wr_len_i,
input fifo_ddr_wr_wr_en_i,
output fifo_ddr_wdata_almost_full_o,
output fifo_ddr_wdata_full_o,
input [DATA_WIDTH-1:0] fifo_ddr_wdata_i,
input [DATA_WIDTH/8-1:0] fifo_ddr_wstrb_i,
input fifo_ddr_wdata_wr_en_i
);
wire fifo_ddr_rd_addr_empty;
wire fifo_ddr_rd_len_empty;
wire fifo_ddr_rd_rd_en;
wire [ADDR_WIDTH-1:0] fifo_ddr_rd_addr;
wire fifo_ddr_rd_addr_v;
wire [7:0] fifo_ddr_rd_len;
wire fifo_ddr_rd_len_v;
wire fifo_ddr_rdata_almost_full;
wire fifo_ddr_rdata_full;
wire fifo_ddr_rdata_wr_en;
wire [DATA_WIDTH-1:0] fifo_ddr_rdata;
wire fifo_ddr_wr_addr_empty;
wire fifo_ddr_wr_len_empty;
wire fifo_ddr_wr_rd_en;
wire [ADDR_WIDTH-1:0] fifo_ddr_wr_addr;
wire fifo_ddr_wr_addr_v;
wire [7:0] fifo_ddr_wr_len;
wire fifo_ddr_wr_len_v;
wire fifo_ddr_wdata_empty;
wire fifo_ddr_wstrb_empty;
wire fifo_ddr_wdata_rd_en;
wire [DATA_WIDTH-1:0] fifo_ddr_wdata;
wire fifo_ddr_wdata_v;
wire [DATA_WIDTH/8-1:0] fifo_ddr_wstrb;
wire fifo_ddr_wstrb_v;
wire fifo_ddr_rd_addr_almost_full;
wire fifo_ddr_rd_addr_full;
wire fifo_ddr_rd_len_almost_full;
wire fifo_ddr_rd_len_full;
wire fifo_ddr_wr_addr_almost_full;
wire fifo_ddr_wr_addr_full;
wire fifo_ddr_wr_len_almost_full;
wire fifo_ddr_wr_len_full;
wire fifo_ddr_wdata_almost_full;
wire fifo_ddr_wdata_full;
wire fifo_ddr_wstrb_almost_full;
wire fifo_ddr_wstrb_full;
assign fifo_ddr_rd_almost_full_o = fifo_ddr_rd_addr_almost_full & fifo_ddr_rd_len_almost_full;
assign fifo_ddr_rd_full_o = fifo_ddr_rd_addr_full & fifo_ddr_rd_len_full;
assign fifo_ddr_wr_almost_full_o = fifo_ddr_wr_addr_almost_full & fifo_ddr_wr_len_almost_full;
assign fifo_ddr_wr_full_o = fifo_ddr_wr_addr_full & fifo_ddr_wr_len_full;
assign fifo_ddr_wdata_almost_full_o = fifo_ddr_wdata_almost_full & fifo_ddr_wstrb_almost_full;
assign fifo_ddr_wdata_full_o = fifo_ddr_wdata_full & fifo_ddr_wstrb_full;
ddr_axi_m_rd #(
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH )
)
ddr_axi_m_rd_inst (
.ui_clk_i (ui_clk_i ),
.ui_rst_i (ui_rst_i ),
.m_axi_arid_o (m_axi_arid_o ),
.m_axi_araddr_o (m_axi_araddr_o ),
.m_axi_arlen_o (m_axi_arlen_o ),
.m_axi_arsize_o (m_axi_arsize_o ),
.m_axi_arburst_o (m_axi_arburst_o ),
.m_axi_arlock_o (m_axi_arlock_o ),
.m_axi_arcache_o (m_axi_arcache_o ),
.m_axi_arprot_o (m_axi_arprot_o ),
.m_axi_arvalid_o (m_axi_arvalid_o ),
.m_axi_arready_i (m_axi_arready_i ),
.m_axi_rready_o (m_axi_rready_o ),
.m_axi_rid_i (m_axi_rid_i ),
.m_axi_rdata_i (m_axi_rdata_i ),
.m_axi_rresp_i (m_axi_rresp_i ),
.m_axi_rlast_i (m_axi_rlast_i ),
.m_axi_rvalid_i (m_axi_rvalid_i ),
.fifo_ddr_rd_empty_i (fifo_ddr_rd_addr_empty & fifo_ddr_rd_len_empty),
.fifo_ddr_rd_rd_en_o (fifo_ddr_rd_rd_en ),
.fifo_ddr_rd_v_i (fifo_ddr_rd_addr_v & fifo_ddr_rd_len_v ),
.fifo_ddr_rd_addr_i (fifo_ddr_rd_addr ),
.fifo_ddr_rd_len_i (fifo_ddr_rd_len ),
.fifo_ddr_rdata_almost_full_i (fifo_ddr_rdata_almost_full ),
.fifo_ddr_rdata_wr_en_o (fifo_ddr_rdata_wr_en ),
.fifo_ddr_rdata_o (fifo_ddr_rdata )
);
ddr_axi_m_wr #(
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH )
)
ddr_axi_m_wr_inst (
.ui_clk_i (ui_clk_i),
.ui_rst_i (ui_rst_i),
.m_axi_awid_o (m_axi_awid_o ),
.m_axi_awaddr_o (m_axi_awaddr_o ),
.m_axi_awlen_o (m_axi_awlen_o ),
.m_axi_awsize_o (m_axi_awsize_o ),
.m_axi_awburst_o (m_axi_awburst_o ),
.m_axi_awlock_o (m_axi_awlock_o ),
.m_axi_awcache_o (m_axi_awcache_o ),
.m_axi_awprot_o (m_axi_awprot_o ),
.m_axi_awvalid_o (m_axi_awvalid_o ),
.m_axi_awready_i (m_axi_awready_i ),
.m_axi_wdata_o (m_axi_wdata_o ),
.m_axi_wstrb_o (m_axi_wstrb_o ),
.m_axi_wlast_o (m_axi_wlast_o ),
.m_axi_wvalid_o (m_axi_wvalid_o ),
.m_axi_wready_i (m_axi_wready_i ),
.m_axi_bready_o (m_axi_bready_o ),
.m_axi_bid_i (m_axi_bid_i ),
.m_axi_bresp_i (m_axi_bresp_i ),
.m_axi_bvalid_i (m_axi_bvalid_i ),
.fifo_ddr_wr_empty_i (fifo_ddr_wr_addr_empty & fifo_ddr_wr_len_empty),
.fifo_ddr_wr_rd_en_o (fifo_ddr_wr_rd_en ),
.fifo_ddr_wr_v_i (fifo_ddr_wr_addr_v & fifo_ddr_wr_len_v),
.fifo_ddr_wr_addr_i (fifo_ddr_wr_addr ),
.fifo_ddr_wr_len_i (fifo_ddr_wr_len ),
.fifo_ddr_wdata_empty_i (fifo_ddr_wdata_empty & fifo_ddr_wstrb_empty),
.fifo_ddr_wdata_rd_en_o (fifo_ddr_wdata_rd_en ),
.fifo_ddr_wdata_v_i (fifo_ddr_wdata_v & fifo_ddr_wstrb_v),
.fifo_ddr_wdata_i (fifo_ddr_wdata ),
.fifo_ddr_wstrb_i (fifo_ddr_wstrb )
);
fifo_ddr_addr fifo_ddr_rd_addr_inst(
.wr_clk (sys_clk_i),
.rd_clk (ui_clk_i),
.rst (sys_rst_i),
.almost_full (fifo_ddr_rd_addr_almost_full),
.full (fifo_ddr_rd_addr_full),
.din (fifo_ddr_rd_addr_i),
.wr_en (fifo_ddr_rd_wr_en_i),
.empty (fifo_ddr_rd_addr_empty),
.dout (fifo_ddr_rd_addr),
.valid (fifo_ddr_rd_addr_v),
.rd_en (fifo_ddr_rd_rd_en)
);
fifo_ddr_len fifo_ddr_rd_len_inst(
.wr_clk (sys_clk_i),
.rd_clk (ui_clk_i),
.rst (sys_rst_i),
.almost_full (fifo_ddr_rd_len_almost_full),
.full (fifo_ddr_rd_len_full),
.din (fifo_ddr_rd_len_i),
.wr_en (fifo_ddr_rd_wr_en_i),
.empty (fifo_ddr_rd_len_empty),
.dout (fifo_ddr_rd_len),
.valid (fifo_ddr_rd_len_v),
.rd_en (fifo_ddr_rd_rd_en)
);
fifo_ddr_data fifo_ddr_rdata_inst(
.wr_clk (ui_clk_i),
.rd_clk (sys_clk_i),
.rst (sys_rst_i),
.almost_full (fifo_ddr_rdata_almost_full),
.full (fifo_ddr_rdata_full),
.din (fifo_ddr_rdata),
.wr_en (fifo_ddr_rdata_wr_en),
.empty (fifo_ddr_rdata_empty_o),
.dout (fifo_ddr_rdata_o),
.valid (fifo_ddr_rdata_v_o),
.rd_en (fifo_ddr_rdata_rd_en_i)
);
fifo_ddr_addr fifo_ddr_wr_addr_inst(
.wr_clk (sys_clk_i),
.rd_clk (ui_clk_i),
.rst (sys_rst_i),
.almost_full (fifo_ddr_wr_addr_almost_full),
.full (fifo_ddr_wr_addr_full),
.din (fifo_ddr_wr_addr_i),
.wr_en (fifo_ddr_wr_wr_en_i),
.empty (fifo_ddr_wr_addr_empty),
.dout (fifo_ddr_wr_addr),
.valid (fifo_ddr_wr_addr_v),
.rd_en (fifo_ddr_wr_rd_en)
);
fifo_ddr_len fifo_ddr_wr_len_inst(
.wr_clk (sys_clk_i),
.rd_clk (ui_clk_i),
.rst (sys_rst_i),
.almost_full (fifo_ddr_wr_len_almost_full),
.full (fifo_ddr_wr_len_full),
.din (fifo_ddr_wr_len_i),
.wr_en (fifo_ddr_wr_wr_en_i),
.empty (fifo_ddr_wr_len_empty),
.dout (fifo_ddr_wr_len),
.valid (fifo_ddr_wr_len_v),
.rd_en (fifo_ddr_wr_rd_en)
);
fifo_ddr_data fifo_ddr_wdata_inst(
.wr_clk (sys_clk_i),
.rd_clk (ui_clk_i),
.rst (sys_rst_i),
.almost_full (fifo_ddr_wdata_almost_full),
.full (fifo_ddr_wdata_full),
.din (fifo_ddr_wdata_i),
.wr_en (fifo_ddr_wdata_wr_en_i),
.empty (fifo_ddr_wdata_empty),
.dout (fifo_ddr_wdata),
.valid (fifo_ddr_wdata_v),
.rd_en (fifo_ddr_wdata_rd_en)
);
fifo_ddr_strb fifo_ddr_wstrb_inst(
.wr_clk (sys_clk_i),
.rd_clk (ui_clk_i),
.rst (sys_rst_i),
.almost_full (fifo_ddr_wstrb_almost_full),
.full (fifo_ddr_wstrb_full),
.din (fifo_ddr_wstrb_i),
.wr_en (fifo_ddr_wdata_wr_en_i),
.empty (fifo_ddr_wstrb_empty),
.dout (fifo_ddr_wstrb),
.valid (fifo_ddr_wstrb_v),
.rd_en (fifo_ddr_wdata_rd_en)
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/03/27 16:50:57
// Design Name:
// Module Name: ddr_axi_m_wr
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ddr_axi_m_wr #(
parameter ADDR_WIDTH = 33, // 8GB
parameter DATA_WIDTH = 128 // lowest 3 bits should be 0
)
(
input ui_clk_i,
input ui_rst_i,
// Master Interface Write Address Ports
output [3:0] m_axi_awid_o,
output [ADDR_WIDTH-1:0] m_axi_awaddr_o,
output [7:0] m_axi_awlen_o,
output [2:0] m_axi_awsize_o,
output [1:0] m_axi_awburst_o,
output [0:0] m_axi_awlock_o,
output [3:0] m_axi_awcache_o,
output [2:0] m_axi_awprot_o,
output m_axi_awvalid_o,
input m_axi_awready_i,
// Master Interface Write Data Ports
output [DATA_WIDTH-1:0] m_axi_wdata_o,
output [DATA_WIDTH/8-1:0] m_axi_wstrb_o,
output m_axi_wlast_o,
output m_axi_wvalid_o,
input m_axi_wready_i,
// Master Interface Write Response Ports
output m_axi_bready_o,
input [3:0] m_axi_bid_i,
input [1:0] m_axi_bresp_i,
input m_axi_bvalid_i,
input fifo_ddr_wr_empty_i,
output fifo_ddr_wr_rd_en_o,
input fifo_ddr_wr_v_i,
input [ADDR_WIDTH-1:0] fifo_ddr_wr_addr_i,
input [7:0] fifo_ddr_wr_len_i,
input fifo_ddr_wdata_empty_i,
input fifo_ddr_wdata_rd_en_o,
input fifo_ddr_wdata_v_i,
input [DATA_WIDTH-1:0] fifo_ddr_wdata_i,
input [DATA_WIDTH/8-1:0] fifo_ddr_wstrb_i
);
localparam [2:0] RSIZE_VALUE = $clog2(DATA_WIDTH/8);
localparam [6:0]
S_WR_IDLE = 7'b0000001,
S_WR_ADDR = 7'b0000010,
S_WR_ADDR_WAIT = 7'b0000100,
S_WR_DATA_START = 7'b0001000,
S_WR_DATA = 7'b0010000,
S_WR_DATA_WAIT = 7'b0100000,
S_WR_DONE = 7'b1000000;
reg [6:0] c_state;
reg [6:0] n_state;
reg fifo_ddr_wr_rd_en;
reg [ADDR_WIDTH-1:0] fifo_ddr_wr_addr;
reg [7:0] fifo_ddr_wr_len;
reg fifo_ddr_wr_v;
reg fifo_ddr_wdata_rd_en;
reg [DATA_WIDTH-1:0] fifo_ddr_wdata;
reg [DATA_WIDTH/8-1:0] fifo_ddr_wstrb;
reg fifo_ddr_wdata_v;
reg wr_data_cnt_clr;
reg wr_data_cnt_inc;
reg [7:0] wr_data_cnt;
reg m_axi_wlast;
reg m_axi_bready;
wire wr_data_cnt_is_thresh;
assign m_axi_awid_o = 4'b0;
assign m_axi_awaddr_o = fifo_ddr_wr_addr;
assign m_axi_awlen_o = fifo_ddr_wr_len - 1'b1;
assign m_axi_awsize_o = RSIZE_VALUE;
assign m_axi_awburst_o = 2'b01; // INCR Mode
assign m_axi_awlock_o = 1'b0;
assign m_axi_awcache_o = 4'b0000;
assign m_axi_awprot_o = 3'b000;
assign m_axi_awvalid_o = fifo_ddr_wr_v;
assign m_axi_wdata_o = fifo_ddr_wdata;
assign m_axi_wstrb_o = fifo_ddr_wstrb;
assign m_axi_wlast_o = m_axi_wlast;
assign m_axi_wvalid_o = fifo_ddr_wdata_v;
assign m_axi_bready_o = m_axi_bready;
assign fifo_ddr_wr_rd_en_o = fifo_ddr_wr_rd_en;
assign fifo_ddr_wdata_rd_en_o = fifo_ddr_wdata_rd_en;
assign wr_data_cnt_is_thresh = (wr_data_cnt == fifo_ddr_wr_len);
always @(posedge ui_clk_i or posedge ui_rst_i) begin
if(ui_rst_i) begin
c_state <= S_WR_IDLE;
end
else begin
c_state <= n_state;
end
end
always @(*) begin
fifo_ddr_wr_rd_en = 1'b0;
fifo_ddr_wr_v = 1'b0;
fifo_ddr_wdata_v = 1'b0;
wr_data_cnt_clr = 1'b0;
wr_data_cnt_inc = 1'b0;
m_axi_bready = 1'b0;
m_axi_wlast = 1'b0;
fifo_ddr_wdata_rd_en = 1'b0;
n_state = S_WR_IDLE;
case(c_state)
S_WR_IDLE: begin
wr_data_cnt_clr = 1'b1;
fifo_ddr_wr_addr = 33'b0;
fifo_ddr_wr_len = 8'b0;
if (!fifo_ddr_wr_empty_i) begin
fifo_ddr_wr_rd_en = 1'b1;
n_state = S_WR_ADDR;
end else begin
n_state = S_WR_IDLE;
end
end
S_WR_ADDR: begin
fifo_ddr_wr_addr = fifo_ddr_wr_addr_i;
fifo_ddr_wr_len = fifo_ddr_wr_len_i;
fifo_ddr_wr_v = 1'b1;
if(m_axi_awready_i) begin
n_state = S_WR_DATA_START;
end
else begin
n_state = S_WR_ADDR_WAIT;
end
end
S_WR_ADDR_WAIT: begin
fifo_ddr_wr_v = 1'b1;
if(m_axi_awready_i) begin
n_state = S_WR_DATA_START;
end
else begin
n_state = S_WR_ADDR_WAIT;
end
end
S_WR_DATA_START: begin
if (!fifo_ddr_wdata_empty_i) begin
fifo_ddr_wdata_rd_en = 1'b1;
wr_data_cnt_inc = 1'b1;
n_state = S_WR_DATA;
end else begin
n_state = S_WR_DATA_START;
end
end
S_WR_DATA: begin
fifo_ddr_wdata = fifo_ddr_wdata_i;
fifo_ddr_wstrb = fifo_ddr_wstrb_i;
fifo_ddr_wdata_v = 1'b1;
casex({wr_data_cnt_is_thresh, m_axi_wready_i, !fifo_ddr_wdata_empty_i})
3'b00x: begin
n_state = S_WR_DATA_WAIT;
end
3'b010: begin
n_state = S_WR_DATA_START;
end
3'b011: begin
fifo_ddr_wdata_v = 1'b1;
fifo_ddr_wdata_rd_en = 1'b1;
wr_data_cnt_inc = 1'b1;
n_state = S_WR_DATA;
end
3'b11x: begin
m_axi_wlast = 1'b1;
n_state = S_WR_DONE;
end
3'b10x: begin
n_state = S_WR_DATA_WAIT;
end
endcase
end
S_WR_DATA_WAIT: begin
fifo_ddr_wdata_v = 1'b1;
casex({wr_data_cnt_is_thresh, m_axi_wready_i, !fifo_ddr_wdata_empty_i})
3'b00x: begin
n_state = S_WR_DATA_WAIT;
end
3'b010: begin
n_state = S_WR_DATA_START;
end
3'b011: begin
fifo_ddr_wdata_rd_en = 1'b1;
wr_data_cnt_inc = 1'b1;
n_state = S_WR_DATA;
end
3'b11x: begin
m_axi_wlast = 1'b1;
n_state = S_WR_DONE;
end
3'b10x: begin
n_state = S_WR_DATA_WAIT;
end
endcase
end
S_WR_DONE: begin
if (m_axi_bvalid_i && m_axi_bresp_i == 2'b00) begin
m_axi_bready = 1'b1;
n_state = S_WR_IDLE;
end else begin
n_state = S_WR_DONE;
end
end
default: begin
n_state = S_WR_IDLE;
end
endcase
end
always @(posedge ui_clk_i or posedge ui_rst_i) begin
if(ui_rst_i) begin
wr_data_cnt <= 8'b0;
end
else if(wr_data_cnt_clr)begin
wr_data_cnt <= 8'b0;
end
else if(wr_data_cnt_inc) begin
wr_data_cnt <= wr_data_cnt + 1'b1;
end
else begin
wr_data_cnt <= wr_data_cnt;
end
end
endmodule