FPGALab/ddr3_general_design
7
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
1 Commit 1 Branch 0 Tags
66ef804e176a0419b5605d94e56c71cf52ad5bcb
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
UnbalancedCat 66ef804e17 v2.0_fifo_interface
2025-04-27 19:10:44 +08:00
ddr3_general_design.srcs
v2.0_fifo_interface
2025-04-27 19:10:44 +08:00
.gitignore
v2.0_fifo_interface
2025-04-27 19:10:44 +08:00
ddr3_general_design.xpr
v2.0_fifo_interface
2025-04-27 19:10:44 +08:00
Description
基于 ax7325t 的通用 axi 转 fifo 的 mig ddr3 控制接口项目模板
59 MiB
Languages
Verilog 100%