137 lines
3.3 KiB
Verilog
137 lines
3.3 KiB
Verilog
`timescale 1ns / 1ps
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`include "cpu.h"
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module forward(
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input clk,
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input [`DS_TO_FW_BUS_WD - 1:0] ds_to_fw_bus,
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input [`ES_TO_FW_BUS_WD - 1:0] es_to_fw_bus,
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input [`MS_TO_FW_BUS_WD - 1:0] ms_to_fw_bus,
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output [`FW_TO_ES_BUS_WD - 1:0] fw_to_es_bus
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);
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wire [4:0] ds_rs1;
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wire [4:0] ds_rs2;
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wire [4:0] es_rs2;
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wire [4:0] es_rd ;
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wire es_MemWr;
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wire es_RegWr;
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wire [4:0] ms_rd ;
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wire ms_RegWr;
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wire [1:0] BusAFw;
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wire [1:0] BusBFw;
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wire DiSrc;
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reg [`FW_TO_ES_BUS_WD - 1:0] fw_to_es_bus_r;
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assign {ds_rs1, ds_rs2} = ds_to_fw_bus;
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assign {es_rs2, es_rd , es_RegWr, es_MemWr} = es_to_fw_bus;
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assign {ms_rd , ms_RegWr } = ms_to_fw_bus;
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assign BusAFw[0] = ms_RegWr && (ms_rd != 5'b0) && (es_rd != ds_rs1) && (ms_rd == ds_rs1);
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assign BusAFw[1] = es_RegWr && (es_rd != 5'b0) && (es_rd == ds_rs1) ;
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assign BusBFw[0] = ms_RegWr && (ms_rd != 5'b0) && (es_rd != ds_rs2) && (ms_rd == ds_rs2);
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assign BusBFw[1] = es_RegWr && (es_rd != 5'b0) && (es_rd == ds_rs2) ;
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assign DiSrc = ms_RegWr && (ms_rd != 5'b0) && (ms_rd == es_rs2) && es_MemWr ;
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always @(posedge clk) begin
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fw_to_es_bus_r <= {BusAFw, BusBFw, DiSrc};
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end
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assign fw_to_es_bus = fw_to_es_bus_r;
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endmodule
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module loaduse(
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input clk,
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input reset,
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input [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus,
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input [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus,
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output ds_stall,
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output es_flush
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);
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wire [4:0] ds_sr1;
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wire [4:0] ds_sr2;
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wire [4:0] es_Load;
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wire [4:0] es_rd;
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wire stall;
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assign {ds_sr1, ds_sr2 } = ds_to_lu_bus;
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assign {es_rd , es_Load} = es_to_lu_bus;
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assign stall = ^es_Load &&
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(((ds_sr1 == es_rd) && (ds_sr1 != 5'b0)) || ((ds_sr2 == es_rd) && (ds_sr2 != 5'b0)));
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assign ds_stall = stall;
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assign es_flush = stall;
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endmodule
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module piplinectr(
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input clk,
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input reset,
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input lu_flush,
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input dh_flush,
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input dh_stall,
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output fs_stall,
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output fs_flush,
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output ds_flush,
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output es_flush,
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output ms_flush,
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output ws_flush
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);
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reg [7:0] flush;
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reg [1:0] stall;
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always @(posedge clk) begin
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if(reset) begin
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flush <= 5'b0;
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end
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else if(lu_flush) begin
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flush <= {flush[6] , lu_flush , flush[4:0], 1'b0};
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end
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else if(dh_flush) begin
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flush <= {flush[6:5], {3{dh_flush}}, flush[1:0], 1'b0};
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end
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else begin
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flush <= {flush[6:0] , 1'b0};
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end
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if(reset) begin
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stall <= 2'b0;
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end
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else if(dh_stall) begin
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stall <= {stall[0], dh_stall};
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end
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else begin
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stall <= {stall[0], 1'b0};
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end
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end
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assign {ws_flush,
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ms_flush,
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es_flush,
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ds_flush,
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fs_flush} = flush[7:3] | {2'b0, lu_flush, 2'b0} | {3'b0, dh_flush, dh_flush};
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assign fs_stall = ^stall | dh_stall;
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endmodule
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