228 lines
7.1 KiB
Verilog
228 lines
7.1 KiB
Verilog
`timescale 1ns / 1ps
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`include "cpu.h"
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module cpu_top(
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input clk,
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input resetn,
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// inst ram interface
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output instr_ram_en,
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output [ 3:0] instr_ram_wen,
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output [31:0] instr_ram_addr,
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output [31:0] instr_ram_wdata,
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input [31:0] instr_ram_rdata,
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// data ram interface
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output data_ram_en,
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output [ 3:0] data_ram_wen,
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output [31:0] data_ram_addr,
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output [31:0] data_ram_wdata,
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input [31:0] data_ram_rdata,
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// trace debug interface
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output [31:0] debug_wb_pc,
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output [ 3:0] debug_wb_rf_wen,
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output [ 4:0] debug_wb_rf_wnum,
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output [31:0] debug_wb_rf_wdata,
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input [ 4:0] rf_raddr,
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output [31:0] rf_rdata
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);
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reg reset;
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always @(posedge clk) reset <= ~resetn;
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wire ds_allowin;
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wire es_allowin;
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wire ms_allowin;
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wire ws_allowin;
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wire fs_to_ds_valid;
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wire ds_to_es_valid;
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wire es_to_ms_valid;
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wire ms_to_ws_valid;
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wire [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus;
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wire [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
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wire [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus;
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wire [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;
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wire [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
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wire [`BR_BUS_WD -1:0] br_bus;
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wire [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus;
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wire [`ES_TO_FW_BUS_WD -1:0] es_to_fw_bus;
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wire [`MS_TO_FW_BUS_WD -1:0] ms_to_fw_bus;
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wire [`FW_TO_ES_BUS_WD -1:0] fw_to_es_bus;
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wire [`MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
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wire [`WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
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wire [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus;
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wire [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus;
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wire lu_stall;
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wire dh_flush;
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wire dh_stall;
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wire fs_stall;
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wire fs_flush;
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wire ds_flush;
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wire es_flush;
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wire ms_flush;
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wire ws_flush;
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// IF stage
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if_stage if_stage(
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.clk (clk ),
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.reset (reset ),
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.fs_flush (fs_flush ),
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.fs_stall (fs_stall ),
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//allowin
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.ds_allowin (ds_allowin ),
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//brbus
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.br_bus (br_bus ),
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//outputs
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.fs_to_ds_valid (fs_to_ds_valid ),
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.fs_to_ds_bus (fs_to_ds_bus ),
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// inst ram interface
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.instr_ram_en (instr_ram_en ),
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.instr_ram_wen (instr_ram_wen ),
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.instr_ram_addr (instr_ram_addr ),
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.instr_ram_wdata(instr_ram_wdata),
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.instr_ram_rdata(instr_ram_rdata)
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);
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// ID stage
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id_stage id_stage(
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.clk (clk ),
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.reset (reset ),
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.ds_flush (ds_flush ),
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.stall (lu_stall ),
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//allowin
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.es_allowin (es_allowin ),
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.ds_allowin (ds_allowin ),
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//from fs
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.fs_to_ds_valid (fs_to_ds_valid ),
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.fs_to_ds_bus (fs_to_ds_bus ),
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//to es
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.ds_to_es_valid (ds_to_es_valid ),
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.ds_to_es_bus (ds_to_es_bus ),
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//to fw
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.ds_to_fw_bus (ds_to_fw_bus ),
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//to lu
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.ds_to_lu_bus (ds_to_lu_bus ),
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//to rf: for write back
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.ws_to_rf_bus (ws_to_rf_bus ),
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//to pipctr
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.dh_flush (dh_flush ),
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.dh_stall (dh_stall ),
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.rf_raddr (rf_raddr ),
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.rf_rdata (rf_rdata )
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);
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// EXE stage
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exe_stage exe_stage(
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.clk (clk ),
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.reset (reset ),
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.es_flush (es_flush ),
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//allowin
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.ms_allowin (ms_allowin ),
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.es_allowin (es_allowin ),
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//from ds
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.ds_to_es_valid (ds_to_es_valid ),
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.ds_to_es_bus (ds_to_es_bus ),
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//from ms
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.ms_to_es_bus (ms_to_es_bus ),
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//from ws
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.ws_to_es_bus (ws_to_es_bus ),
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//from fw
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.fw_to_es_bus (fw_to_es_bus ),
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//to lu
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.es_to_lu_bus (es_to_lu_bus ),
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//to fw
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.es_to_fw_bus (es_to_fw_bus ),
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//to ms
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.es_to_ms_valid (es_to_ms_valid ),
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.es_to_ms_bus (es_to_ms_bus ),
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// data ram interface
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.data_ram_en (data_ram_en ),
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.data_ram_wen (data_ram_wen ),
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.data_ram_addr (data_ram_addr ),
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.data_ram_wdata (data_ram_wdata )
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);
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// MEM stage
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mem_stage mem_stage(
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.clk (clk ),
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.reset (reset ),
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.ms_flush (ms_flush ),
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//allowin
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.ws_allowin (ws_allowin ),
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.ms_allowin (ms_allowin ),
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//from es
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.es_to_ms_valid (es_to_ms_valid ),
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.es_to_ms_bus (es_to_ms_bus ),
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//to fs
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.br_bus (br_bus ),
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//to es: for forward
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.ms_to_es_bus (ms_to_es_bus ),
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//to fw
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.ms_to_fw_bus (ms_to_fw_bus ),
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//to ws
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.ms_to_ws_valid (ms_to_ws_valid ),
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.ms_to_ws_bus (ms_to_ws_bus ),
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//from data-ram
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.data_ram_rdata (data_ram_rdata)
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);
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// WB stage
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wb_stage wb_stage(
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.clk (clk ),
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.reset (reset ),
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.ws_flush (ws_flush ),
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//allowin
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.ws_allowin (ws_allowin ),
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//from ms
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.ms_to_ws_valid (ms_to_ws_valid ),
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.ms_to_ws_bus (ms_to_ws_bus ),
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//to rf: for write back
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.ws_to_rf_bus (ws_to_rf_bus ),
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//to es: for forward
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.ws_to_es_bus (ws_to_es_bus ),
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//trace debug interface
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.debug_wb_pc (debug_wb_pc ),
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.debug_wb_rf_wen (debug_wb_rf_wen ),
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.debug_wb_rf_wnum (debug_wb_rf_wnum ),
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.debug_wb_rf_wdata(debug_wb_rf_wdata)
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);
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// Forward
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forward u_forward(
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.clk (clk ),
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.ds_to_fw_bus (ds_to_fw_bus),
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.es_to_fw_bus (es_to_fw_bus),
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.ms_to_fw_bus (ms_to_fw_bus),
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.fw_to_es_bus (fw_to_es_bus)
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);
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// Load Use
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loaduse u_loaduse(
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.clk (clk ),
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.reset (reset ),
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.ds_to_lu_bus (ds_to_lu_bus),
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.es_to_lu_bus (es_to_lu_bus),
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.ds_stall (lu_stall ),
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.es_flush (lu_flush )
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);
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piplinectr u_piplinectr(
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.clk (clk ),
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.reset (reset ),
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.lu_flush (lu_flush),
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.dh_flush (dh_flush),
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.dh_stall (dh_stall),
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.fs_stall (fs_stall),
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.fs_flush (fs_flush),
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.ds_flush (ds_flush),
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.es_flush (es_flush),
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.ms_flush (ms_flush),
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.ws_flush (ws_flush)
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);
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endmodule
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