96 lines
2.4 KiB
Verilog
96 lines
2.4 KiB
Verilog
`timescale 1ns / 1ps
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module soc_top(
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input resetn,
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input clk,
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input [ 4:0] switch,
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output [15:0] led
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);
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wire cpu_clk;
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reg cpu_resetn;
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wire [31:0] led32;
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assign led = led32[15:0];
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always @(posedge cpu_clk)
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begin
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cpu_resetn <= resetn;
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end
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pll u_pll(
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.clk_in1 (clk),
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.clk_out1 (cpu_clk)
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);
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//cpu instr ram
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wire cpu_instr_en;
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wire [ 3:0] cpu_instr_wen;
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wire [31:0] cpu_instr_addr;
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wire [31:0] cpu_instr_wdata;
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wire [31:0] cpu_instr_rdata;
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//cpu data ram
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wire cpu_data_en;
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wire [ 3:0] cpu_data_wen;
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wire [31:0] cpu_data_addr;
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wire [31:0] cpu_data_wdata;
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wire [31:0] cpu_data_rdata;
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//debug signals
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wire [31:0] debug_wb_pc;
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wire [ 3:0] debug_wb_rf_wen;
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wire [ 4:0] debug_wb_rf_wnum;
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wire [31:0] debug_wb_rf_wdata;
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cpu_top cpu(
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.clk (cpu_clk ),
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.resetn (cpu_resetn),
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.instr_ram_en (cpu_instr_en ),
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.instr_ram_wen (cpu_instr_wen ),
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.instr_ram_addr (cpu_instr_addr ),
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.instr_ram_wdata (cpu_instr_wdata),
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.instr_ram_rdata (cpu_instr_rdata),
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.data_ram_en (cpu_data_en ),
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.data_ram_wen (cpu_data_wen ),
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.data_ram_addr (cpu_data_addr ),
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.data_ram_wdata (cpu_data_wdata),
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.data_ram_rdata (cpu_data_rdata),
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//debug
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.debug_wb_pc (debug_wb_pc ),
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.debug_wb_rf_wen (debug_wb_rf_wen ),
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.debug_wb_rf_wnum (debug_wb_rf_wnum ),
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.debug_wb_rf_wdata(debug_wb_rf_wdata),
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.rf_raddr (switch ),
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.rf_rdata (led32 )
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);
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//instr ram
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instr_ram instr_ram
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(
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.clka (cpu_clk ),
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.ena (cpu_instr_en ),
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.wea (cpu_instr_wen ), //3:0
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.addra (cpu_instr_addr[17:2]), //15:0
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.dina (cpu_instr_wdata ), //31:0
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.douta (cpu_instr_rdata ) //31:0
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);
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//data ram
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data_ram data_ram
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(
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.clka (cpu_clk ),
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.ena (cpu_data_en ),
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.wea (cpu_data_wen ), //3:0
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.addra (cpu_data_addr[17:2] ), //15:0
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.dina (cpu_data_wdata ), //31:0
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.douta (cpu_data_rdata ) //31:0
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);
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endmodule
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