107 lines
3.3 KiB
Verilog
107 lines
3.3 KiB
Verilog
`timescale 1ns / 1ps
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module alu(
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input [10:0] alu_op ,
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input [31:0] alu_src1 ,
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input [31:0] alu_src2 ,
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output [31:0] alu_result,
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output Carry ,
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output Sign ,
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output Overflow ,
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output Zero
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);
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wire op_lui;
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wire op_add;
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wire op_sub;
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wire op_or;
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wire op_slt;
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wire op_sltu;
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wire op_xor;
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wire op_and;
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wire op_sll;
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wire op_srl;
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wire op_sra;
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assign op_lui = alu_op[ 0];
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assign op_add = alu_op[ 1];
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assign op_sub = alu_op[ 2];
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assign op_slt = alu_op[ 3];
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assign op_sltu = alu_op[ 4];
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assign op_xor = alu_op[ 5];
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assign op_or = alu_op[ 6];
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assign op_and = alu_op[ 7];
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assign op_sll = alu_op[ 8];
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assign op_srl = alu_op[ 9];
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assign op_sra = alu_op[10];
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wire [31:0] lui_result;
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wire [31:0] add_sub_result;
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wire [31:0] slt_result;
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wire [31:0] sltu_result;
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wire [31:0] xor_result;
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wire [31:0] or_result;
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wire [31:0] and_result;
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wire [31:0] sll_result;
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wire [31:0] sr64_result;
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wire [31:0] sr_result;
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// 32-bit adder
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wire [31:0] adder_a;
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wire [31:0] adder_b;
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wire adder_cin;
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wire [31:0] adder_result;
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wire adder_cout;
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assign adder_a = alu_src1;
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assign adder_b = (op_sub | op_slt | op_sltu) ? ~alu_src2 : alu_src2;
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assign adder_cin = (op_sub | op_slt | op_sltu) ? 1'b1 : 1'b0;
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assign {adder_cout, adder_result} = adder_a + adder_b + adder_cin;
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// ADD, SUB result
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assign add_sub_result = adder_result;
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// SLT result
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assign slt_result[31:1] = 31'b0;
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assign slt_result[0] = (alu_src1[31] & ~alu_src2[31])
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| ((alu_src1[31] ~^ alu_src2[31]) & adder_result[31]);
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// SLTU result
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assign sltu_result[31:1] = 31'b0;
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assign sltu_result[0] = ~adder_cout;
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// bitwise operation
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assign or_result = alu_src1 | alu_src2;
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assign and_result = alu_src1 & alu_src2;
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assign xor_result = alu_src1 ^ alu_src2;
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assign lui_result = alu_src2;
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// SLL result
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assign sll_result = alu_src1 << alu_src2[4:0];
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// SRL, SRA result
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assign sr64_result = {{32{op_sra & alu_src1[31]}}, alu_src1[31:0]} >> alu_src2[4:0];
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assign sr_result = sr64_result[31:0];
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// final result mux
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assign alu_result = ({32{op_add|op_sub}} & add_sub_result)
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| ({32{op_slt }} & slt_result)
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| ({32{op_sltu }} & sltu_result)
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| ({32{op_or }} & or_result)
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| ({32{op_xor }} & xor_result)
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| ({32{op_and }} & and_result)
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| ({32{op_lui }} & lui_result)
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| ({32{op_sll }} & sll_result)
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| ({32{op_srl|op_sra}} & sr_result);
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assign Carry = op_sub ^ adder_cout;
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assign Sign = alu_result[31];
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assign Overflow = (op_add|op_sub) ? ( adder_a[31] & adder_b[31] & adder_cout)
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| (~adder_a[31] & ~adder_b[31] & ~adder_cout)
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: 1'b0;
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assign Zero = (alu_result == 32'b0);
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endmodule
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