42 lines
983 B
Verilog
42 lines
983 B
Verilog
`timescale 1ns / 1ps
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module cpu_tb(
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);
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reg resetn;
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reg clk;
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wire [31:0] debug_wb_pc;
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wire [ 3:0] debug_wb_rf_wen;
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wire [ 4:0] debug_wb_rf_wnum;
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wire [31:0] debug_wb_rf_wdata;
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initial
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begin
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clk = 1'b0;
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resetn = 1'b0;
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#20;
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resetn = 1'b1;
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#5000;
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//$finish;
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end
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always #5 clk=~clk;
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soc_top u_soc_top(
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.resetn (resetn ),
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.clk (clk )
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);
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//debug signals
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assign debug_wb_pc = u_soc_top.debug_wb_pc;
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assign debug_wb_rf_wen = u_soc_top.debug_wb_rf_wen;
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assign debug_wb_rf_wnum = u_soc_top.debug_wb_rf_wnum;
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assign debug_wb_rf_wdata = u_soc_top.debug_wb_rf_wdata;
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always @(posedge clk) begin
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$display("PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h",
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debug_wb_pc, debug_wb_rf_wnum, debug_wb_rf_wdata);
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end
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endmodule
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