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153
cpu_rv32i.srcs/sources_1/new/ctrsignal.v
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153
cpu_rv32i.srcs/sources_1/new/ctrsignal.v
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`timescale 1ns / 1ps
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module ctrsignal(
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input [ 6:0] OP,
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input [ 2:0] func3,
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input [ 6:0] func7,
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output [ 4:0] ExtOp,
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output [ 1:0] ALUAsrc,
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output [ 2:0] ALUBsrc,
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output [10:0] ALUctr,
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output RegWr,
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output MemtoReg,
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output MemWr,
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output [ 5:0] Branch,
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output [ 1:0] Jump,
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output [ 2:0] Store,
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output [ 4:0] Load,
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output shamt
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);
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wire u_type;
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wire j_type;
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wire s_type;
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wire i_type;
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wire b_type;
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wire r_type;
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wire instr_lui ;
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wire instr_auipc;
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wire instr_jal ;
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wire instr_jalr ;
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wire instr_beq ;
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wire instr_bne ;
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wire instr_blt ;
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wire instr_bge ;
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wire instr_bltu ;
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wire instr_bgeu ;
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wire instr_lb ;
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wire instr_lh ;
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wire instr_lw ;
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wire instr_lbu ;
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wire instr_lhu ;
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wire instr_sb ;
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wire instr_sh ;
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wire instr_sw ;
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wire instr_addi ;
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wire instr_slti ;
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wire instr_sltiu;
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wire instr_xori ;
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wire instr_ori ;
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wire instr_andi ;
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wire instr_slli ;
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wire instr_srli ;
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wire instr_srai ;
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wire instr_add ;
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wire instr_sub ;
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wire instr_sll ;
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wire instr_slt ;
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wire instr_sltu ;
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wire instr_xor ;
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wire instr_srl ;
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wire instr_sra ;
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wire instr_or ;
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wire instr_and ;
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assign u_type = (OP == 7'b0110111) || (OP == 7'b0010111);
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assign j_type = (OP == 7'b1101111);
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assign s_type = (OP == 7'b0100011);
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assign i_type = (OP == 7'b1100111) || (OP == 7'b0000011) ||(OP == 7'b0010011);
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assign b_type = (OP == 7'b1100011);
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assign r_type = (OP == 7'b0110011);
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assign instr_lui = (OP == 7'b0110111) ;
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assign instr_auipc = (OP == 7'b0010111) ;
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assign instr_jal = (OP == 7'b1101111) ;
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assign instr_jalr = (OP == 7'b1100111) ;
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assign instr_beq = b_type & (func3 == 3'b000) ;
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assign instr_bne = b_type & (func3 == 3'b001) ;
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assign instr_blt = b_type & (func3 == 3'b100) ;
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assign instr_bge = b_type & (func3 == 3'b101) ;
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assign instr_bltu = b_type & (func3 == 3'b110) ;
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assign instr_bgeu = b_type & (func3 == 3'b111) ;
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assign instr_lb = (OP == 7'b0000011) & (func3 == 3'b000) ;
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assign instr_lh = (OP == 7'b0000011) & (func3 == 3'b001) ;
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assign instr_lw = (OP == 7'b0000011) & (func3 == 3'b010) ;
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assign instr_lbu = (OP == 7'b0000011) & (func3 == 3'b100) ;
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assign instr_lhu = (OP == 7'b0000011) & (func3 == 3'b101) ;
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assign instr_sb = s_type & (func3 == 3'b000) ;
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assign instr_sh = s_type & (func3 == 3'b001) ;
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assign instr_sw = s_type & (func3 == 3'b010) ;
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assign instr_addi = (OP == 7'b0010011) & (func3 == 3'b000) ;
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assign instr_slti = (OP == 7'b0010011) & (func3 == 3'b010) ;
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assign instr_sltiu = (OP == 7'b0010011) & (func3 == 3'b011) ;
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assign instr_xori = (OP == 7'b0010011) & (func3 == 3'b100) ;
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assign instr_ori = (OP == 7'b0010011) & (func3 == 3'b110) ;
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assign instr_andi = (OP == 7'b0010011) & (func3 == 3'b111) ;
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assign instr_slli = (OP == 7'b0010011) & (func3 == 3'b001) & (func7 == 7'b0000000);
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assign instr_srli = (OP == 7'b0010011) & (func3 == 3'b101) & (func7 == 7'b0000000);
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assign instr_srai = (OP == 7'b0010011) & (func3 == 3'b101) & (func7 == 7'b0100000);
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assign instr_add = r_type & (func3 == 3'b000) & (func7 == 7'b0000000);
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assign instr_sub = r_type & (func3 == 3'b000) & (func7 == 7'b0100000);
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assign instr_sll = r_type & (func3 == 3'b001) & (func7 == 7'b0000000);
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assign instr_slt = r_type & (func3 == 3'b010) & (func7 == 7'b0000000);
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assign instr_sltu = r_type & (func3 == 3'b011) & (func7 == 7'b0000000);
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assign instr_xor = r_type & (func3 == 3'b100) & (func7 == 7'b0000000);
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assign instr_srl = r_type & (func3 == 3'b101) & (func7 == 7'b0000000);
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assign instr_sra = r_type & (func3 == 3'b101) & (func7 == 7'b0100000);
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assign instr_or = r_type & (func3 == 3'b110) & (func7 == 7'b0000000);
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assign instr_and = r_type & (func3 == 3'b111) & (func7 == 7'b0000000);
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assign ExtOp = {u_type,
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j_type,
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s_type,
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i_type,
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b_type
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};
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assign ALUAsrc = { j_type | instr_auipc, // pc
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~j_type & ~instr_auipc // rs1_value
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};
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assign ALUBsrc = { u_type | s_type | i_type, // imm
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j_type, // 4
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b_type | r_type // rs2_value
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};
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assign ALUctr[ 0] = instr_lui ;
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assign ALUctr[ 1] = instr_lb | instr_lh | instr_lw | instr_lbu
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| instr_lhu | instr_sb | instr_sh | instr_sw
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| instr_addi | instr_add | instr_auipc | j_type ;
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assign ALUctr[ 2] = instr_sub | b_type ;
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assign ALUctr[ 3] = instr_slt | instr_slti ;
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assign ALUctr[ 4] = instr_sltu | instr_sltiu ;
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assign ALUctr[ 5] = instr_xori | instr_xor ;
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assign ALUctr[ 6] = instr_ori | instr_or ;
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assign ALUctr[ 7] = instr_and | instr_andi ;
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assign ALUctr[ 8] = instr_slli | instr_sll ;
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assign ALUctr[ 9] = instr_srli | instr_srl ;
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assign ALUctr[10] = instr_srai | instr_sra ;
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assign RegWr = ~(instr_sw | instr_sh | instr_sb) & ~b_type;
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assign MemtoReg = instr_lb | instr_lh | instr_lw | instr_lbu | instr_lhu;
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assign MemWr = s_type;
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assign Branch = { instr_bgeu, instr_bltu , instr_bge, instr_blt , instr_bne, instr_beq};
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assign Jump = { instr_jalr, instr_jal};
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assign Load = { instr_lhu , instr_lbu , instr_lw , instr_lh , instr_lb};
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assign Store = { instr_sw , instr_sh , instr_sb};
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assign shamt = instr_slli | instr_srli | instr_srai;
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endmodule
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