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包焕垲
2023-02-28 09:10:42 +08:00
commit a657a360bf
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37
cpu_rv32i.srcs/sources_1/ip/instr_ram/bubble_sort_instr.coe Normal file
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cpu_rv32i.srcs/sources_1/ip/instr_ram/instr_ram.xci Normal file
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"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
}
},
"RST.ARESETN": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
}
},
"BRAM_PORTA": {
"vlnv": "xilinx.com:interface:bram:1.0",
"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
"mode": "slave",
"parameters": {
"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_static_object": false } ],
"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
},
"port_maps": {
"ADDR": [ { "physical_name": "addra" } ],
"CLK": [ { "physical_name": "clka" } ],
"DIN": [ { "physical_name": "dina" } ],
"DOUT": [ { "physical_name": "douta" } ],
"EN": [ { "physical_name": "ena" } ],
"WE": [ { "physical_name": "wea" } ]
}
}
},
"memory_maps": {
"S_1": {
"address_blocks": {
"Mem0": {
"base_address": "0",
"range": "4096",
"usage": "memory",
"access": "read-write",
"parameters": {
"OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
"OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
}
}
}
}
}
}
}
}

14
cpu_rv32i.srcs/sources_1/ip/instr_ram/raw 测试代码.txt Normal file
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@@ -0,0 +1,14 @@
lw x3, 0x0(x0) # 00002183 读取主存地址0x0000处的n到x3
add x3, x3, x3 # 003181B3
slt x4, x0 ,x3 # 00302233 将x4的值通过比较指令赋为 1
ori x5, x1, 0x1 # 00106293 x5内容（循环变量i）为1
ori x2, x1, 0x1 # 00106113 x2内容（循环增量）为1
loop:
add x4, x4, x5 # 00520233 将i加到x4（累加）
beq x5, x3, finish # 00328663 若x5=n，则跳出循环
add x5, x5, x2 # 002282b3 x5=x5+1
jal x0, loop # FF5FF06F 无条件跳转到loop执行
finish:
sw x4, 0x4(x0) # 00402223 将累加结果保存到0x0001单元
end:
jal x0, end # 0000006F 无条件跳转到end执行

14
cpu_rv32i.srcs/sources_1/ip/instr_ram/raw_instr.coe Normal file
View File

@@ -0,0 +1,14 @@
MEMORY_INITIALIZATION_RADIX=16;
MEMORY_INITIALIZATION_VECTOR=
00002183,
003181B3,
00302233,
00106293,
00106113,
00520233,
00328663,
002282b3,
FF5FF06F,
00402223,
0000006F;

20
cpu_rv32i.srcs/sources_1/ip/instr_ram/test.coe Normal file
View File

@@ -0,0 +1,20 @@
MEMORY_INITIALIZATION_RADIX=16;
MEMORY_INITIALIZATION_VECTOR=
80100537,
01300593,
3A050513,
FFF00813,
00000713,
00050793,
02B75263,
0007A683,
0047A603,
00170713,
00D65663,
00C7A023,
00D7A223,
00478793,
FEB742E3,
FFF58593,
FD0598E3,
00008067;