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f87199d467a8aa880a0bf06277f139e7208caa86
neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank
History
UnbalancedCat f87199d467 [Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
..
hdl
[Modified] Debug & board test with cache & pass n58 with 40 MHz
2023-07-22 14:56:53 +08:00
synth
[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test
2023-07-31 16:05:29 +08:00
data_bram_bank_ooc.xdc
[Modified] Debug & board test with cache & pass n58 with 40 MHz
2023-07-22 14:56:53 +08:00
data_bram_bank_sim_netlist.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
data_bram_bank_sim_netlist.vhdl
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
data_bram_bank_stub.v
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
data_bram_bank_stub.vhdl
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
data_bram_bank.dcp
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
data_bram_bank.veo
[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test
2023-07-31 16:05:29 +08:00
data_bram_bank.vho
[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test
2023-07-31 16:05:29 +08:00
data_bram_bank.xci
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
data_bram_bank.xml
[Modified] pre submit file organization
2023-08-04 16:10:30 +08:00
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