14 lines
278 B
Verilog
14 lines
278 B
Verilog
module mmu (
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input [31:0] addr_i,
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output [31:0] addr_o,
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output cache_v
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);
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wire [31:0] dmw0;
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assign dmw0 = 0;
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assign cache_v = (dmw0[31:29] == addr_i[31:29]);
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assign addr_o = cache_v? {dmw0[27:25],addr_i[28:0]} : addr_i;
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endmodule |