109 lines
4.1 KiB
Verilog
109 lines
4.1 KiB
Verilog
module forward
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#(
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parameter DEST_WD = 5,
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parameter RESULT_WD = 32,
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parameter CTRL_WD = 2
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)
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(
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input clk ,
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input reset,
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input flush,
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input [ 5:0] stall,
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input [ 4:0] rj,
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input [ 4:0] rkd,
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input es_reg_we ,
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input [DEST_WD -1:0] es_dest ,
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input [RESULT_WD -1:0] es_result ,
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input [CTRL_WD -1:0] es_ctrl ,
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input dts_reg_we,
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input [DEST_WD -1:0] dts_dest ,
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input [RESULT_WD -1:0] dts_result,
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input [CTRL_WD -1:0] dts_ctrl ,
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input ms1_reg_we,
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input [DEST_WD -1:0] ms1_dest ,
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input [RESULT_WD -1:0] ms1_result,
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input [CTRL_WD -1:0] ms1_ctrl ,
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input ms2_reg_we,
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input [DEST_WD -1:0] ms2_dest ,
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input [RESULT_WD -1:0] ms2_result,
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input [CTRL_WD -1:0] ms2_ctrl ,
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output reg src1_is_forward,
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output reg src2_is_forward,
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output reg [RESULT_WD -1:0] src1_forward_result,
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output reg [RESULT_WD -1:0] src2_forward_result,
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output stallreq_forward
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);
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wire src1_is_es_result;
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wire src1_is_dts_result;
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wire src1_is_ms1_result;
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wire src1_is_ms2_result;
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wire src2_is_es_result;
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wire src2_is_dts_result;
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wire src2_is_ms1_result;
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wire src2_is_ms2_result;
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wire src1_is_forward_w;
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wire src2_is_forward_w;
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wire [RESULT_WD -1:0] src1_forward_result_w;
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wire [RESULT_WD -1:0] src2_forward_result_w;
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assign src1_is_es_result = es_reg_we & (rj == es_dest ) & (rj != 0);
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assign src1_is_dts_result = dts_reg_we & (rj == dts_dest) & (rj != 0);
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assign src1_is_ms1_result = ms1_reg_we & (rj == ms1_dest) & (rj != 0);
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assign src1_is_ms2_result = ms2_reg_we & (rj == ms2_dest) & (rj != 0);
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assign src2_is_es_result = es_reg_we & (rkd == es_dest ) & (rkd != 0);
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assign src2_is_dts_result = dts_reg_we & (rkd == dts_dest) & (rkd != 0);
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assign src2_is_ms1_result = ms1_reg_we & (rkd == ms1_dest) & (rkd != 0);
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assign src2_is_ms2_result = ms2_reg_we & (rkd == ms2_dest) & (rkd != 0);
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assign src1_is_forward_w = src1_is_es_result | src1_is_dts_result | src1_is_ms1_result | src1_is_ms2_result;
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assign src2_is_forward_w = src2_is_es_result | src2_is_dts_result | src2_is_ms1_result | src2_is_ms2_result;
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assign src1_forward_result_w = src1_is_es_result ? es_result :
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src1_is_dts_result ? dts_result :
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src1_is_ms1_result ? ms1_result :
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src1_is_ms2_result ? ms2_result :
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32'b0;
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assign src2_forward_result_w = src2_is_es_result ? es_result :
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src2_is_dts_result ? dts_result :
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src2_is_ms1_result ? ms1_result :
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src2_is_ms2_result ? ms2_result :
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32'b0;
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assign stallreq_forward = ((|es_ctrl ) & (src1_is_es_result | src2_is_es_result ))
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| ((|dts_ctrl) & (src1_is_dts_result | src2_is_dts_result))
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| ((|ms1_ctrl) & (src1_is_ms1_result | src2_is_ms1_result));
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//| ((|ms2_ctrl) & (src1_is_ms2_result | src2_is_ms2_result));
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always @(posedge clk) begin
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if (reset) begin
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src1_is_forward <= 0;
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src2_is_forward <= 0;
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src1_forward_result <= 0;
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src2_forward_result <= 0;
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end
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else if (stall[2] & (!stall[3])) begin
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src1_is_forward <= 0;
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src2_is_forward <= 0;
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src1_forward_result <= 0;
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src2_forward_result <= 0;
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end
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else if (!stall[2]) begin
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src1_is_forward <= src1_is_forward_w;
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src2_is_forward <= src2_is_forward_w;
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src1_forward_result <= src1_forward_result_w;
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src2_forward_result <= src2_forward_result_w;
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end
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end
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endmodule |