52 lines
1.2 KiB
Verilog
52 lines
1.2 KiB
Verilog
module div(
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input clk,
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input reset,
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output stallreq,
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input in_valid,
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output out_valid,
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input [31:0] a,
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input [31:0] b,
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output reg [31:0] quotient, //商
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output reg [31:0] remainder //余数
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);
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reg [ 5:0] cnt;
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wire [31:0] sub_result;
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wire carry;
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wire [31:0] temp;
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always @ (posedge clk) begin
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if (reset) begin
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cnt <= 0;
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end
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else if (cnt != 0) begin
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cnt <= cnt -1;
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end
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else if (in_valid) begin
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cnt <= 32;
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end
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end
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assign temp = {remainder[30:0],quotient[31]};
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assign carry = temp < b ? 0 : 1;
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assign sub_result = carry ? temp - b : temp;
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always @ (posedge clk) begin
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if (reset) begin
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quotient <= 0;
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remainder <= 0;
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end
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else if (cnt != 0) begin
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{remainder, quotient} <= {sub_result, quotient[30:0], carry};
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end
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else if (in_valid) begin
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quotient <= a;
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remainder <= 0;
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end
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end
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assign out_valid = (cnt==0);
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assign stallreq = in_valid | (~(cnt==0));
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endmodule |