UnbalancedCat/neulacpu

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bLueriVerLHR 32e948a593 [Add] import xv6-riscv and submodules

2023-07-20 17:47:07 +08:00

[Add] add icache dcache axi & pass test n46(before syscall)

2023-07-20 17:19:04 +08:00

[Add] import xv6-riscv and submodules

2023-07-20 17:47:07 +08:00

loongarch64-linux-gnu @ f535a6f47e

[Add] import xv6-riscv and submodules

2023-07-20 17:47:07 +08:00

nscscc-team-la32r @ 0ef5a87bed

[Add] import xv6-riscv and submodules

2023-07-20 17:47:07 +08:00

.gitignore

[Modified] Fix louduse

2023-06-08 16:27:48 +08:00

.gitmodules

[Add] import xv6-riscv and submodules

2023-07-20 17:47:07 +08:00

Makefile

[Add] import xv6-riscv and submodules

2023-07-20 17:47:07 +08:00

README.md

[Modified] rm redundant files

2023-07-20 17:22:27 +08:00

README.md

LoongArch CPU

龙芯处理器设计

文件组织建议

文件夹名称	文件夹用处
lacpu	龙芯处理器设计 Verilog

Languages

C 47.1%

Verilog 44.2%

Tcl 5.4%

Assembly 1.8%

Makefile 0.9%

Other 0.6%