31 lines
781 B
Verilog
Executable File
31 lines
781 B
Verilog
Executable File
module regfile(
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input clk,
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// READ PORT 1
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input [ 4:0] raddr1,
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output [31:0] rdata1,
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// READ PORT 2
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input [ 4:0] raddr2,
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output [31:0] rdata2,
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// WRITE PORT
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input we, //write enable, HIGH valid
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input [ 4:0] waddr,
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input [31:0] wdata
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);
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reg [31:0] rf[31:0];
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//WRITE
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always @(posedge clk) begin
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if (we) rf[waddr]<= wdata;
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end
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//READ OUT 1
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assign rdata1 = (raddr1==5'b0 ) ? 32'b0 :
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(raddr1==waddr) ? wdata :
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rf[raddr1];
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//READ OUT 2
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assign rdata2 = (raddr2==5'b0 ) ? 32'b0 :
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(raddr2==waddr) ? wdata :
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rf[raddr2];
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endmodule |