154 lines
5.0 KiB
Verilog
Executable File
154 lines
5.0 KiB
Verilog
Executable File
module soc_lite_top
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(
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input resetn,
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input clk,
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output [15:0] pc
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);
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//debug signals
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wire [31:0] debug_wb_pc;
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wire [3 :0] debug_wb_rf_wen;
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wire [4 :0] debug_wb_rf_wnum;
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wire [31:0] debug_wb_rf_wdata;
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//clk and resetn
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wire cpu_clk;
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reg cpu_resetn;
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assign pc = debug_wb_pc[15:0];
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assign cpu_clk = clk;
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always @(posedge cpu_clk)
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begin
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cpu_resetn <= resetn;
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end
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//cpu inst sram
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wire cpu_inst_en;
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wire [3 :0] cpu_inst_wen;
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wire [31:0] cpu_inst_addr;
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wire [31:0] cpu_inst_wdata;
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wire [31:0] cpu_inst_rdata;
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//cpu data sram
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wire cpu_data_en;
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wire [3 :0] cpu_data_wen;
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wire [31:0] cpu_data_addr;
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wire [31:0] cpu_data_wdata;
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wire [31:0] cpu_data_rdata;
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//div
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wire [31:0] div_divisor_data;
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wire div_divisor_valid;
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wire div_divisor_ready;
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wire [31:0] div_dividend_data;
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wire div_dividend_valid;
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wire div_dividend_ready;
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wire div_dout_valid;
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wire [63:0] div_dout_data;
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//divu
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wire [31:0] divu_divisor_data;
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wire divu_divisor_valid;
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wire divu_divisor_ready;
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wire [31:0] divu_dividend_data;
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wire divu_dividend_valid;
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wire divu_dividend_ready;
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wire divu_dout_valid;
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wire [63:0] divu_dout_data;
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//cpu
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mycpu_top cpu(
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.clk (cpu_clk ),
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.resetn (cpu_resetn), //low active
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.inst_sram_en (cpu_inst_en ),
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.inst_sram_wen (cpu_inst_wen ),
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.inst_sram_addr (cpu_inst_addr ),
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.inst_sram_wdata (cpu_inst_wdata),
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.inst_sram_rdata (cpu_inst_rdata),
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.data_sram_en (cpu_data_en ),
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.data_sram_wen (cpu_data_wen ),
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.data_sram_addr (cpu_data_addr ),
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.data_sram_wdata (cpu_data_wdata),
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.data_sram_rdata (cpu_data_rdata),
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//div
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.div_divisor_data (div_divisor_data ),
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.div_divisor_valid (div_divisor_valid ),
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.div_divisor_ready (div_divisor_ready ),
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.div_dividend_data (div_dividend_data ),
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.div_dividend_valid (div_dividend_valid ),
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.div_dividend_ready (div_dividend_ready ),
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.div_dout_valid (div_dout_valid ),
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.div_dout_data (div_dout_data ),
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//divu
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.divu_divisor_data (divu_divisor_data ),
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.divu_divisor_valid (divu_divisor_valid ),
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.divu_divisor_ready (divu_divisor_ready ),
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.divu_dividend_data (divu_dividend_data ),
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.divu_dividend_valid(divu_dividend_valid),
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.divu_dividend_ready(divu_dividend_ready),
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.divu_dout_valid (divu_dout_valid ),
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.divu_dout_data (divu_dout_data ),
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//debug
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.debug_wb_pc (debug_wb_pc ),
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.debug_wb_rf_wen (debug_wb_rf_wen ),
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.debug_wb_rf_wnum (debug_wb_rf_wnum ),
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.debug_wb_rf_wdata(debug_wb_rf_wdata)
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);
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`ifdef DPIC
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`else
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//inst ram
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inst_ram inst_ram
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(
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.clka (cpu_clk ),
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.ena (cpu_inst_en ),
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.wea (cpu_inst_wen ), //3:0
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.addra (cpu_inst_addr[17:2]), //15:0
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.dina (cpu_inst_wdata ), //31:0
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.douta (cpu_inst_rdata ) //31:0
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);
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//data ram
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data_ram data_ram
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(
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.clka (cpu_clk ),
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.ena (cpu_data_en ),
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.wea (cpu_data_wen ), //3:0
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.addra (cpu_data_addr[17:2]), //15:0
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.dina (cpu_data_wdata ), //31:0
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.douta (cpu_data_rdata ) //31:0
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);
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//div
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div div(
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.aclk (cpu_clk ),
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.s_axis_divisor_tdata (div_divisor_data ),
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.s_axis_divisor_tvalid (div_divisor_valid ),
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.s_axis_divisor_tready (div_divisor_ready ),
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.s_axis_dividend_tdata (div_dividend_data ),
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.s_axis_dividend_tvalid (div_dividend_valid ),
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.s_axis_dividend_tready (div_dividend_ready ),
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.m_axis_dout_tvalid (div_dout_valid ),
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.m_axis_dout_tdata (div_dout_data )
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);
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//divu
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divu divu(
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.aclk (cpu_clk ),
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.s_axis_divisor_tdata (divu_divisor_data ),
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.s_axis_divisor_tvalid (divu_divisor_valid ),
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.s_axis_divisor_tready (divu_divisor_ready ),
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.s_axis_dividend_tdata (divu_dividend_data ),
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.s_axis_dividend_tvalid (divu_dividend_valid),
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.s_axis_dividend_tready (divu_dividend_ready),
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.m_axis_dout_tvalid (divu_dout_valid ),
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.m_axis_dout_tdata (divu_dout_data )
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);
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`endif
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endmodule
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