39 lines
1.1 KiB
Verilog
39 lines
1.1 KiB
Verilog
`include "mycpu.v"
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module loaduse(
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input clk,
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input reset,
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input [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus,
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input [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus,
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output loaduse
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);
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wire [4:0] ds_rf_raddr1;
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wire [4:0] ds_rf_raddr2;
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wire [4:0] es_load_op;
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wire [4:0] es_dest;
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reg [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus_reg;
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reg [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus_reg;
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wire loaduse;
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always @(posedge clk) begin
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if(reset) begin
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ds_to_lu_bus_reg <= 0;
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es_to_lu_bus_reg <= 0;
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end
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else begin
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ds_to_lu_bus_reg <= ds_to_lu_bus;
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es_to_lu_bus_reg <= es_to_lu_bus;
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end
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end
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assign {ds_rf_rdata1, ds_rf_rdata2} = ds_to_lu_bus_reg;
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assign {es_dest , es_load_op } = es_to_lu_bus_reg;
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assign loaduse = ^es_load_op &&
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(((ds_rf_rdata1 == es_dest) && (ds_rf_rdata1 != 5'b0)) || ((ds_rf_rdata2 == es_dest) && (ds_rf_rdata2 != 5'b0)));
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endmodule |