3 Commits

Author	SHA1	Message	Date
UnbalancedCat	27ef99503d	[Add] add ext_int	2023-07-23 01:59:53 +08:00
UnbalancedCat	4c9c2ddd78	[Modified] Debug & board test with cache & pass n58 with 40 MHz	2023-07-22 14:56:53 +08:00
UnbalancedCat	a755aae99e	[Modified] Switch soc_top&board to axi&xc7a200t	2023-07-20 21:40:21 +08:00