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[Backup] ready for switching to 7-stage pipline

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包焕垲
2023-07-25 21:06:44 +08:00
parent 0352651836
commit bf2dd4655b
6 changed files with 87 additions and 22 deletions
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7
lacpu/rtl/mycpu/mycpu_core.v
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@@ -56,6 +56,8 @@ module mycpu_core
wire [BR_BUS_WD -1:0] br_bus;
wire flush;
//wire stallreq_fs_for_cache;
//wire stallreq_es_for_cache;
wire stallreq_es;
wire stallreq_ds;
wire [ 5:0] stall;
@@ -75,6 +77,7 @@ module mycpu_core
.flush (flush ),
.stall (stall ),
.new_pc (new_pc ),
//.stallreq_fs_for_cache (stallreq_fs_for_cache ),
.fs_to_ds_bus (fs_to_ds_bus ),
.br_bus (br_bus ),
.inst_sram_en (inst_sram_en ),
@@ -111,6 +114,8 @@ module mycpu_core
.ms_to_es_bus (ms_to_es_bus ),
.ws_to_es_bus (ws_to_es_bus ),
//.stallreq_es_for_cache (stallreq_es_for_cache),
.br_bus (br_bus ),
.data_sram_en (data_sram_en ),
@@ -157,6 +162,8 @@ module mycpu_core
pip_ctrl pip_ctrl(
.reset (reset ),
.except_en (except_en ),
//.stallreq_fs_for_cache (stallreq_fs_for_cache ),
//.stallreq_es_for_cache (stallreq_es_for_cache ),
.stallreq_ds (stallreq_ds ),
.stallreq_es (stallreq_es ),
.stallreq_axi (stallreq_cache ), // TODO!