diff --git a/lacpu/rtl/mycpu/exe_stage.v b/lacpu/rtl/mycpu/exe_stage.v
index 1b477a8..29421c6 100644
--- a/lacpu/rtl/mycpu/exe_stage.v
+++ b/lacpu/rtl/mycpu/exe_stage.v
@@ -13,6 +13,7 @@ module exe_stage
input [ 5:0] stall,
output stallreq_es,
+ //output stallreq_es_for_cache,
input [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus,
output [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus,
@@ -28,6 +29,7 @@ module exe_stage
);
reg [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus_r;
+ reg stallreq_es_for_cache_r;
wire [63:0] csr_vec;
wire [63:0] csr_vec_temp;
@@ -252,5 +254,31 @@ module exe_stage
assign csr_vec = {csr_vec_temp[63:8], excp_ale, csr_vec_temp[6:0]};
assign stallreq_es = stallreq_for_mul_div;
+
+ // always @(posedge clk) begin
+ // if (reset) begin
+ // stallreq_es_for_cache_r <= 1'b0;
+ // end
+ // else if (flush) begin
+ // stallreq_es_for_cache_r <= 1'b0;
+ // end
+ // //nop, id stall and ex not stall
+ // else if (stall[2] & (!stall[3])) begin
+ // stallreq_es_for_cache_r <= 1'b0;
+ // end
+ // //nop, id not stall and br_bus[32]
+ // else if (!stall[2] & br_flush) begin
+ // stallreq_es_for_cache_r <= 1'b0;
+ // end
+ // // id not stall so can go on
+ // else if (!stall[2] & (|load_op | |store_op)) begin
+ // stallreq_es_for_cache_r <= 1'b1;
+ // end
+ // else begin
+ // stallreq_es_for_cache_r <= 1'b0;
+ // end
+ // end
+
+ // assign stallreq_es_for_cache = stallreq_es_for_cache_r;
endmodule
\ No newline at end of file
diff --git a/lacpu/rtl/mycpu/if_stage.v b/lacpu/rtl/mycpu/if_stage.v
index 5906502..fb73b4e 100644
--- a/lacpu/rtl/mycpu/if_stage.v
+++ b/lacpu/rtl/mycpu/if_stage.v
@@ -12,6 +12,8 @@ module if_stage
input [31:0] new_pc,
+ //output stallreq_fs_for_cache,
+
output inst_sram_en ,
output [ 3:0] inst_sram_we ,
output [31:0] inst_sram_addr ,
@@ -26,6 +28,8 @@ module if_stage
reg excp_adef;
reg [31:0] csr_vec_h;
+ reg stallreq_fs_for_cache_r;
+
wire [31:0] seq_pc;
wire [31:0] next_pc;
@@ -66,6 +70,22 @@ module if_stage
assign seq_pc = fs_pc + 3'h4;
assign next_pc = br_taken ? br_target : seq_pc;
+ // always @ (posedge clk) begin
+ // if (reset) begin
+ // stallreq_fs_for_cache_r <= 1'b0;
+ // end
+ // else if (flush) begin
+ // stallreq_fs_for_cache_r <= 1'b0;
+ // end
+ // else if (!stall[0]) begin
+ // stallreq_fs_for_cache_r <= 1'b1;
+ // end
+ // else begin
+ // stallreq_fs_for_cache_r <= 1'b0;
+ // end
+ // end
+
+ // assign stallreq_fs_for_cache = stallreq_fs_for_cache_r & (!br_taken);
assign inst_sram_en = (/*flush |*/ br_taken) ? 1'b0 : pc_valid;
assign inst_sram_we = 4'h0;
diff --git a/lacpu/rtl/mycpu/mycpu_core.v b/lacpu/rtl/mycpu/mycpu_core.v
index ebf5e5c..6b8ebc0 100644
--- a/lacpu/rtl/mycpu/mycpu_core.v
+++ b/lacpu/rtl/mycpu/mycpu_core.v
@@ -56,6 +56,8 @@ module mycpu_core
wire [BR_BUS_WD -1:0] br_bus;
wire flush;
+ //wire stallreq_fs_for_cache;
+ //wire stallreq_es_for_cache;
wire stallreq_es;
wire stallreq_ds;
wire [ 5:0] stall;
@@ -75,6 +77,7 @@ module mycpu_core
.flush (flush ),
.stall (stall ),
.new_pc (new_pc ),
+ //.stallreq_fs_for_cache (stallreq_fs_for_cache ),
.fs_to_ds_bus (fs_to_ds_bus ),
.br_bus (br_bus ),
.inst_sram_en (inst_sram_en ),
@@ -111,6 +114,8 @@ module mycpu_core
.ms_to_es_bus (ms_to_es_bus ),
.ws_to_es_bus (ws_to_es_bus ),
+ //.stallreq_es_for_cache (stallreq_es_for_cache),
+
.br_bus (br_bus ),
.data_sram_en (data_sram_en ),
@@ -157,6 +162,8 @@ module mycpu_core
pip_ctrl pip_ctrl(
.reset (reset ),
.except_en (except_en ),
+ //.stallreq_fs_for_cache (stallreq_fs_for_cache ),
+ //.stallreq_es_for_cache (stallreq_es_for_cache ),
.stallreq_ds (stallreq_ds ),
.stallreq_es (stallreq_es ),
.stallreq_axi (stallreq_cache ), // TODO!
diff --git a/lacpu/rtl/mycpu/pip_ctrl.v b/lacpu/rtl/mycpu/pip_ctrl.v
index c783691..67a153d 100644
--- a/lacpu/rtl/mycpu/pip_ctrl.v
+++ b/lacpu/rtl/mycpu/pip_ctrl.v
@@ -2,6 +2,8 @@
module pip_ctrl(
input reset,
input except_en,
+ input stallreq_fs_for_cache,
+ input stallreq_es_for_cache,
input stallreq_ds,
input stallreq_es,
input stallreq_axi,
@@ -37,6 +39,14 @@ module pip_ctrl(
flush = 0;
stall = `StallBus'b111111;
end
+ // else if(stallreq_fs_for_cache) begin
+ // flush = 0;
+ // stall = `StallBus'b000011;
+ // end
+ // else if(stallreq_es_for_cache) begin
+ // flush = 0;
+ // stall = `StallBus'b011111;
+ // end
// else if(stallreq_cache) begin
// flush = 0;
// stall = `StallBus'b111111;
diff --git a/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci b/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci
index 0b825e4..4a1cc4f 100644
--- a/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci
+++ b/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci
@@ -98,17 +98,17 @@
100.0
0000
0000
- 60.00000
+ 100.00000
0000
0000
100.00000
BUFG
50.0
false
- 60.00000
+ 100.00000
0.000
50.000
- 60.000
+ 100.000
0.000
1
0000
@@ -203,12 +203,12 @@
din
0000
1
- 0.6
- 0.6
- 0.6
- 0.6
- 0.6
- 0.6
+ 1.0
+ 1.0
+ 1.0
+ 1.0
+ 1.0
+ 1.0
dout
drdy
dwe
@@ -251,7 +251,7 @@
FALSE
10.000
10.000
- 15.000
+ 9.000
0.500
0.000
FALSE
@@ -292,7 +292,7 @@
2
Output Output Phase Duty Cycle Pk-to-Pk Phase
Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
- _cpu_clk__60.00000______0.000______50.0______153.276____105.461
+ _cpu_clk__100.00000______0.000______50.0______137.681____105.461
timer_clk__100.00000______0.000______50.0______137.681____105.461
no_CLK_OUT3_output
no_CLK_OUT4_output
@@ -414,11 +414,11 @@
100.0
0.010
BUFG
- 153.276
+ 137.681
false
105.461
50.000
- 60.000
+ 100.000
0.000
1
true
@@ -530,7 +530,7 @@
false
10.000
10.000
- 15
+ 9
0.500
0.000
false
diff --git a/lacpu/run_vivado/la32r/la32r.xpr b/lacpu/run_vivado/la32r/la32r.xpr
index bc5c476..89c0095 100644
--- a/lacpu/run_vivado/la32r/la32r.xpr
+++ b/lacpu/run_vivado/la32r/la32r.xpr
@@ -29,20 +29,20 @@
-
+
-
-
-
-
-
-
-
+
+
+
+
+
+
+