[Backup] ready for switching to 7-stage pipline

lacpu/rtl/mycpu/exe_stage.v

@@ -13,6 +13,7 @@ module exe_stage
     input  [ 5:0] stall,
 
     output        stallreq_es,
+    //output        stallreq_es_for_cache,
 
     input  [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus,    
     output [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus,    
@@ -28,6 +29,7 @@ module exe_stage
 );
 
     reg [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus_r;
+    reg                        stallreq_es_for_cache_r;
 
     wire [63:0] csr_vec;
     wire [63:0] csr_vec_temp;
@@ -252,5 +254,31 @@ module exe_stage
     assign csr_vec = {csr_vec_temp[63:8], excp_ale, csr_vec_temp[6:0]};
 
     assign stallreq_es = stallreq_for_mul_div;
+    
+    // always @(posedge clk) begin
+    //     if (reset) begin
+    //         stallreq_es_for_cache_r <= 1'b0;
+    //     end
+    //     else if (flush) begin
+    //         stallreq_es_for_cache_r <= 1'b0;
+    //     end
+    //     //nop, id stall and ex not stall
+    //     else if (stall[2] & (!stall[3])) begin
+    //         stallreq_es_for_cache_r <= 1'b0;
+    //     end
+    //     //nop, id not stall and br_bus[32]
+    //     else if (!stall[2] & br_flush) begin
+    //         stallreq_es_for_cache_r <= 1'b0;
+    //     end
+    //     // id not stall so can go on
+    //     else if (!stall[2] & (|load_op | |store_op)) begin
+    //         stallreq_es_for_cache_r <= 1'b1;
+    //     end
+    //     else begin
+    //         stallreq_es_for_cache_r <= 1'b0;
+    //     end
+    // end    
+    
+    // assign stallreq_es_for_cache = stallreq_es_for_cache_r;
 
 endmodule

lacpu/rtl/mycpu/if_stage.v

@@ -12,6 +12,8 @@ module if_stage
 
     input  [31:0] new_pc,
 
+    //output        stallreq_fs_for_cache,
+
     output        inst_sram_en   ,
     output [ 3:0] inst_sram_we   ,
     output [31:0] inst_sram_addr ,
@@ -26,6 +28,8 @@ module if_stage
     reg         excp_adef;
     reg  [31:0] csr_vec_h;
 
+    reg         stallreq_fs_for_cache_r;
+
     wire [31:0] seq_pc;
     wire [31:0] next_pc;
 
@@ -66,6 +70,22 @@ module if_stage
     assign seq_pc  = fs_pc + 3'h4;
     assign next_pc = br_taken ? br_target : seq_pc;
 
+    // always @ (posedge clk) begin
+    //     if (reset) begin
+    //         stallreq_fs_for_cache_r <= 1'b0;
+    //     end
+    //     else if (flush) begin
+    //         stallreq_fs_for_cache_r <= 1'b0;
+    //     end
+    //     else if (!stall[0]) begin
+    //         stallreq_fs_for_cache_r <= 1'b1;
+    //     end
+    //     else begin
+    //         stallreq_fs_for_cache_r <= 1'b0;
+    //     end
+    // end
+
+    // assign stallreq_fs_for_cache = stallreq_fs_for_cache_r & (!br_taken);
 
     assign inst_sram_en     = (/*flush |*/ br_taken) ? 1'b0 : pc_valid;
     assign inst_sram_we     = 4'h0;

lacpu/rtl/mycpu/mycpu_core.v

@@ -56,6 +56,8 @@ module mycpu_core
     wire [BR_BUS_WD       -1:0] br_bus;
 
     wire        flush;
+    //wire        stallreq_fs_for_cache;
+    //wire        stallreq_es_for_cache;
     wire        stallreq_es;
     wire        stallreq_ds;
     wire [ 5:0] stall;
@@ -75,6 +77,7 @@ module mycpu_core
         .flush           (flush           ),
         .stall           (stall           ),
         .new_pc          (new_pc          ),
+        //.stallreq_fs_for_cache     (stallreq_fs_for_cache     ),
         .fs_to_ds_bus    (fs_to_ds_bus    ),
         .br_bus          (br_bus          ),
         .inst_sram_en    (inst_sram_en    ),
@@ -111,6 +114,8 @@ module mycpu_core
         .ms_to_es_bus    (ms_to_es_bus    ),    
         .ws_to_es_bus    (ws_to_es_bus    ),
 
+        //.stallreq_es_for_cache (stallreq_es_for_cache),
+
         .br_bus          (br_bus          ),
 
         .data_sram_en    (data_sram_en    ),
@@ -157,6 +162,8 @@ module mycpu_core
     pip_ctrl pip_ctrl(
         .reset           (reset           ),
         .except_en       (except_en       ),
+        //.stallreq_fs_for_cache     (stallreq_fs_for_cache     ),
+        //.stallreq_es_for_cache     (stallreq_es_for_cache     ),
         .stallreq_ds     (stallreq_ds     ),
         .stallreq_es     (stallreq_es     ),
         .stallreq_axi    (stallreq_cache  ), // TODO!

lacpu/rtl/mycpu/pip_ctrl.v

@@ -2,6 +2,8 @@
 module pip_ctrl(
     input  reset,
     input  except_en,
+    input  stallreq_fs_for_cache,
+    input  stallreq_es_for_cache,
     input  stallreq_ds,
     input  stallreq_es,
     input  stallreq_axi,
@@ -37,6 +39,14 @@ module pip_ctrl(
             flush = 0;
             stall = `StallBus'b111111;
         end
+        // else if(stallreq_fs_for_cache) begin
+        //     flush = 0;
+        //     stall = `StallBus'b000011;
+        // end
+        // else if(stallreq_es_for_cache) begin
+        //     flush = 0;
+        //     stall = `StallBus'b011111;
+        // end
         // else if(stallreq_cache) begin
         //     flush = 0;
         //     stall = `StallBus'b111111;