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[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)

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包焕垲
2023-07-29 21:16:28 +08:00
parent 3a070d35fc
commit b38d04cc35
9 changed files with 419 additions and 132 deletions
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54
lacpu/run_vivado/la32r/la32r.xpr
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@@ -36,13 +36,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="24"/>
<Option Name="WTModelSimExportSim" Val="24"/>
<Option Name="WTQuestaExportSim" Val="24"/>
<Option Name="WTIesExportSim" Val="24"/>
<Option Name="WTVcsExportSim" Val="24"/>
<Option Name="WTRivieraExportSim" Val="24"/>
<Option Name="WTActivehdlExportSim" Val="24"/>
<Option Name="WTXSimExportSim" Val="31"/>
<Option Name="WTModelSimExportSim" Val="31"/>
<Option Name="WTQuestaExportSim" Val="31"/>
<Option Name="WTIesExportSim" Val="31"/>
<Option Name="WTVcsExportSim" Val="31"/>
<Option Name="WTRivieraExportSim" Val="31"/>
<Option Name="WTActivehdlExportSim" Val="31"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -135,6 +135,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/mycpu/dt.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/mycpu/exe_stage.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -142,6 +149,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/mycpu/forward.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/mycpu/icache.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -391,10 +405,12 @@
<Runs Version="1" Minor="11">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design">
<Option Id="RepFanoutThreshold">400</Option>
<Option Id="NoCombineLuts">1</Option>
<Option Id="ShregMinSize">5</Option>
</Step>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
@@ -443,16 +459,20 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="opt_design">
<Option Id="Directive">0</Option>
</Step>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design" EnableStepBool="1"/>
<Step Id="route_design"/>
<Step Id="phys_opt_design" EnableStepBool="1">
<Option Id="Directive">0</Option>
</Step>
<Step Id="route_design">
<Option Id="Directive">0</Option>
</Step>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>