diff --git a/lacpu/rtl/mycpu/dt.v b/lacpu/rtl/mycpu/dt.v new file mode 100644 index 0000000..07d97ea --- /dev/null +++ b/lacpu/rtl/mycpu/dt.v @@ -0,0 +1,63 @@ +module dt +#( + parameter ES_TO_DT_BUS_WD = 340, + parameter DT_TO_MS_BUS_WD = 271, + parameter MS_TO_ES_BUS_WD = 38 +) +( + input clk, + input reset, + input flush, + input [ 5:0] stall, + + input [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus, + output [DT_TO_MS_BUS_WD -1:0] dts_to_ms1_bus, + output [MS_TO_ES_BUS_WD -1:0] dts_to_es_bus, + + output data_sram_en, + output [ 3:0] data_sram_we, + output [31:0] data_sram_addr, + output [31:0] data_sram_wdata +); + + reg [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus_r; + + wire reg_we; + wire [ 4:0] dest; + wire [31:0] es_result; + + assign dts_to_ms1_bus = es_to_dts_bus_r[DT_TO_MS_BUS_WD -1:0]; + + + assign {reg_we , + dest , + es_result + } = es_to_dts_bus_r[133:96]; + + assign {data_sram_en , + data_sram_we , + data_sram_addr , + data_sram_wdata + } = es_to_dts_bus_r[339:271]; + + assign dts_to_es_bus = {reg_we, + dest, + es_result + }; + + always @(posedge clk) begin + if (reset) begin + es_to_dts_bus_r <= 0; + end + else if (flush) begin + es_to_dts_bus_r <= 0; + end + else if(stall[3] & (!stall[4])) begin + es_to_dts_bus_r <= 0; + end + else if(!stall[3]) begin + es_to_dts_bus_r <= es_to_dts_bus; + end + end + +endmodule \ No newline at end of file diff --git a/lacpu/rtl/mycpu/exe_stage.v b/lacpu/rtl/mycpu/exe_stage.v index 0c0dc82..3f94cea 100644 --- a/lacpu/rtl/mycpu/exe_stage.v +++ b/lacpu/rtl/mycpu/exe_stage.v @@ -2,7 +2,7 @@ module exe_stage #( parameter BR_BUS_WD = 33, parameter DS_TO_ES_BUS_WD = 301, - parameter ES_TO_MS_BUS_WD = 271, + parameter ES_TO_DT_BUS_WD = 340, parameter MS_TO_ES_BUS_WD = 38, parameter WS_TO_ES_BUS_WD = 38 ) @@ -16,19 +16,24 @@ module exe_stage //output stallreq_es_for_cache, input [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus, - output [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus, + output [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus, - input [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus, - input [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus, - input [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus, + input src1_is_forward, + input src2_is_forward, + input [31:0] src1_forward_result, + input [31:0] src2_forward_result, + //input [MS_TO_ES_BUS_WD -1:0] dts_to_es_bus, + //input [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus, + //input [MS_TO_ES_BUS_WD -1:0] ms2_to_es_bus, + //input [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus, output [BR_BUS_WD -1:0] br_bus, - input br_taken_buffer, + input br_taken_buffer - output data_sram_en, - output [ 3:0] data_sram_we, - output [31:0] data_sram_addr, - output [31:0] data_sram_wdata + // output data_sram_en, + // output [ 3:0] data_sram_we, + // output [31:0] data_sram_addr, + // output [31:0] data_sram_wdata ); reg [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus_r; @@ -59,12 +64,15 @@ module exe_stage wire [31:0] es_pc; wire [31:0] inst; + wire dts_reg_we; + wire [ 4:0] dts_dest; + wire [31:0] dts_result; wire ms1_reg_we; wire [ 4:0] ms1_dest; wire [31:0] ms1_result; - wire ms_reg_we; - wire [ 4:0] ms_dest; - wire [31:0] ms_result; + wire ms2_reg_we; + wire [ 4:0] ms2_dest; + wire [31:0] ms2_result; wire ws_reg_we; wire [ 4:0] ws_dest; wire [31:0] ws_result; @@ -92,6 +100,11 @@ module exe_stage wire excp_adef; wire excp_ale; + wire data_sram_en; + wire [ 3:0] data_sram_we; + wire [31:0] data_sram_addr; + wire [31:0] data_sram_wdata; + assign {csr_vec_temp ,//300:237 csr_op ,//236:230 csr_wdata_sel ,//229:229 @@ -117,34 +130,43 @@ module exe_stage inst //31 :0 } = ds_to_es_bus_r; - assign {ms1_reg_we, - ms1_dest, - ms1_result - } = ms1_to_es_bus; + // assign {dts_reg_we, + // dts_dest, + // dts_result + // } = dts_to_es_bus; - assign {ms_reg_we, - ms_dest, - ms_result - } = ms_to_es_bus; + // assign {ms1_reg_we, + // ms1_dest, + // ms1_result + // } = ms1_to_es_bus; - assign {ws_reg_we, - ws_dest, - ws_result - } = ws_to_es_bus; + // assign {ms2_reg_we, + // ms2_dest, + // ms2_result + // } = ms2_to_es_bus; - assign es_to_ms1_bus = {csr_vec ,//270:207 - csr_bus ,//206:143 - load_op ,//142:137 - store_op ,//136:134 - reg_we ,//133:133 - dest ,//132:128 - es_result,//127:96 - src1 ,//95 :64 - es_pc ,//63 :32 - inst //31 :0 + // assign {ws_reg_we, + // ws_dest, + // ws_result + // } = ws_to_es_bus; + + assign es_to_dts_bus = {data_sram_en ,//339:339 + data_sram_we ,//338:335 + data_sram_addr ,//334:303 + data_sram_wdata ,//302:271 + csr_vec ,//270:207 + csr_bus ,//206:143 + load_op ,//142:137 + store_op ,//136:134 + reg_we ,//133:133 + dest ,//132:128 + es_result ,//127:96 + src1 ,//95 :64 + es_pc ,//63 :32 + inst //31 :0 }; - assign br_flush = (br_taken & ~(csr_cancel|csr_cancel_reg))/* | br_taken_buffer*/; // TODO! + assign br_flush = (br_taken & ~(csr_cancel|csr_cancel_reg)) | br_taken_buffer; // TODO! assign excp_adef = csr_vec[6]; @@ -156,11 +178,11 @@ module exe_stage ds_to_es_bus_r <= 0; end //nop, id stall and ex not stall - else if (stall[2]&(!stall[3])) begin + else if (stall[2] & (!stall[3])) begin ds_to_es_bus_r <= 0; end //nop, id not stall and br_bus[32] - else if (!stall[2]&br_flush) begin + else if (!stall[2] & br_flush) begin ds_to_es_bus_r <= 0; end // id not stall so can go on @@ -169,13 +191,17 @@ module exe_stage end end - assign src1 = ms1_reg_we & (ms1_dest == rj ) & (rj != 1'b0) ? ms1_result : // TODO! - ms_reg_we & (ms_dest == rj ) & (rj != 1'b0) ? ms_result : - ws_reg_we & (ws_dest == rj ) & (rj != 1'b0) ? ws_result : + assign src1 = //dts_reg_we & (dts_dest == rj ) & (rj != 1'b0) ? dts_result : // TODO! + //ms1_reg_we & (ms1_dest == rj ) & (rj != 1'b0) ? ms1_result : // TODO! + //ms2_reg_we & (ms2_dest == rj ) & (rj != 1'b0) ? ms2_result : + //ws_reg_we & (ws_dest == rj ) & (rj != 1'b0) ? ws_result : + src1_is_forward ? src1_forward_result : rj_value; - assign src2 = ms1_reg_we & (ms1_dest == rkd) & (rkd != 1'b0) ? ms1_result : // TODO! - ms_reg_we & (ms_dest == rkd) & (rkd != 1'b0) ? ms_result : - ws_reg_we & (ws_dest == rkd) & (rkd != 1'b0) ? ws_result : + assign src2 = //dts_reg_we & (dts_dest == rkd) & (rkd != 1'b0) ? dts_result : // TODO! + //ms1_reg_we & (ms1_dest == rkd) & (rkd != 1'b0) ? ms1_result : // TODO! + //ms2_reg_we & (ms2_dest == rkd) & (rkd != 1'b0) ? ms2_result : + //ws_reg_we & (ws_dest == rkd) & (rkd != 1'b0) ? ws_result : + src2_is_forward ? src2_forward_result : rkd_value; assign alu_src1 = src1_is_pc ? es_pc : @@ -257,11 +283,12 @@ module exe_stage alu_result; assign csr_wdata = src2; - assign csr_bus = {csr_we, - csr_wdata_sel, - csr_op, - csr_addr, - csr_wdata + assign csr_bus = {9'b0 ,//63:55 + csr_we ,//54:54 + csr_wdata_sel ,//53:53 + csr_op ,//52:46 + csr_addr ,//45:32 + csr_wdata //31:0 }; assign csr_vec = {csr_vec_temp[63:8], excp_ale, csr_vec_temp[6:0]}; diff --git a/lacpu/rtl/mycpu/forward.v b/lacpu/rtl/mycpu/forward.v new file mode 100644 index 0000000..51d89a1 --- /dev/null +++ b/lacpu/rtl/mycpu/forward.v @@ -0,0 +1,109 @@ +module forward +#( + parameter DEST_WD = 5, + parameter RESULT_WD = 32, + parameter CTRL_WD = 2 +) +( + input clk , + input reset, + + input flush, + input [ 5:0] stall, + + input [ 4:0] rj, + input [ 4:0] rkd, + input es_reg_we , + input [DEST_WD -1:0] es_dest , + input [RESULT_WD -1:0] es_result , + input [CTRL_WD -1:0] es_ctrl , + input dts_reg_we, + input [DEST_WD -1:0] dts_dest , + input [RESULT_WD -1:0] dts_result, + input [CTRL_WD -1:0] dts_ctrl , + input ms1_reg_we, + input [DEST_WD -1:0] ms1_dest , + input [RESULT_WD -1:0] ms1_result, + input [CTRL_WD -1:0] ms1_ctrl , + input ms2_reg_we, + input [DEST_WD -1:0] ms2_dest , + input [RESULT_WD -1:0] ms2_result, + input [CTRL_WD -1:0] ms2_ctrl , + + output reg src1_is_forward, + output reg src2_is_forward, + + output reg [RESULT_WD -1:0] src1_forward_result, + output reg [RESULT_WD -1:0] src2_forward_result, + + output stallreq_forward +); + + wire src1_is_es_result; + wire src1_is_dts_result; + wire src1_is_ms1_result; + wire src1_is_ms2_result; + + wire src2_is_es_result; + wire src2_is_dts_result; + wire src2_is_ms1_result; + wire src2_is_ms2_result; + + wire src1_is_forward_w; + wire src2_is_forward_w; + + wire [RESULT_WD -1:0] src1_forward_result_w; + wire [RESULT_WD -1:0] src2_forward_result_w; + + assign src1_is_es_result = es_reg_we & (rj == es_dest ) & (rj != 0); + assign src1_is_dts_result = dts_reg_we & (rj == dts_dest) & (rj != 0); + assign src1_is_ms1_result = ms1_reg_we & (rj == ms1_dest) & (rj != 0); + assign src1_is_ms2_result = ms2_reg_we & (rj == ms2_dest) & (rj != 0); + + assign src2_is_es_result = es_reg_we & (rkd == es_dest ) & (rkd != 0); + assign src2_is_dts_result = dts_reg_we & (rkd == dts_dest) & (rkd != 0); + assign src2_is_ms1_result = ms1_reg_we & (rkd == ms1_dest) & (rkd != 0); + assign src2_is_ms2_result = ms2_reg_we & (rkd == ms2_dest) & (rkd != 0); + + assign src1_is_forward_w = src1_is_es_result | src1_is_dts_result | src1_is_ms1_result | src1_is_ms2_result; + assign src2_is_forward_w = src2_is_es_result | src2_is_dts_result | src2_is_ms1_result | src2_is_ms2_result; + + assign src1_forward_result_w = src1_is_es_result ? es_result : + src1_is_dts_result ? dts_result : + src1_is_ms1_result ? ms1_result : + src1_is_ms2_result ? ms2_result : + 32'b0; + + assign src2_forward_result_w = src2_is_es_result ? es_result : + src2_is_dts_result ? dts_result : + src2_is_ms1_result ? ms1_result : + src2_is_ms2_result ? ms2_result : + 32'b0; + + assign stallreq_forward = ((|es_ctrl ) & (src1_is_es_result | src2_is_es_result )) + | ((|dts_ctrl) & (src1_is_dts_result | src2_is_dts_result)) + | ((|ms1_ctrl) & (src1_is_ms1_result | src2_is_ms1_result)); + //| ((|ms2_ctrl) & (src1_is_ms2_result | src2_is_ms2_result)); + + always @(posedge clk) begin + if (reset) begin + src1_is_forward <= 0; + src2_is_forward <= 0; + src1_forward_result <= 0; + src2_forward_result <= 0; + end + else if (stall[2] & (!stall[3])) begin + src1_is_forward <= 0; + src2_is_forward <= 0; + src1_forward_result <= 0; + src2_forward_result <= 0; + end + else if (!stall[2]) begin + src1_is_forward <= src1_is_forward_w; + src2_is_forward <= src2_is_forward_w; + src1_forward_result <= src1_forward_result_w; + src2_forward_result <= src2_forward_result_w; + end + end + +endmodule \ No newline at end of file diff --git a/lacpu/rtl/mycpu/mem_stage.v b/lacpu/rtl/mycpu/mem_stage.v index 2b181fe..bbbe7d1 100644 --- a/lacpu/rtl/mycpu/mem_stage.v +++ b/lacpu/rtl/mycpu/mem_stage.v @@ -1,6 +1,6 @@ module mem1_stage #( - parameter ES_TO_MS_BUS_WD = 271, + parameter DT_TO_MS_BUS_WD = 271, parameter MS_TO_ES_BUS_WD = 38 ) ( @@ -9,22 +9,22 @@ module mem1_stage input flush, input [ 5:0] stall, - input [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus, - output [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus, + input [DT_TO_MS_BUS_WD -1:0] dts_to_ms1_bus, + output [DT_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus, output [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus ); -reg [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus_r; +reg [DT_TO_MS_BUS_WD -1:0] dts_to_ms1_bus_r; wire reg_we; wire [ 4:0] dest; wire [31:0] es_result; -assign ms1_to_ms2_bus = es_to_ms1_bus_r; +assign ms1_to_ms2_bus = dts_to_ms1_bus_r; -assign reg_we = es_to_ms1_bus_r[133:133]; -assign dest = es_to_ms1_bus_r[132:128]; -assign es_result = es_to_ms1_bus_r[127:96]; +assign reg_we = dts_to_ms1_bus_r[133:133]; +assign dest = dts_to_ms1_bus_r[132:128]; +assign es_result = dts_to_ms1_bus_r[127:96]; assign ms1_to_es_bus = {reg_we, dest, @@ -33,16 +33,16 @@ assign ms1_to_es_bus = {reg_we, always @(posedge clk) begin if (reset) begin - es_to_ms1_bus_r <= 0; + dts_to_ms1_bus_r <= 0; end else if (flush) begin - es_to_ms1_bus_r <= 0; + dts_to_ms1_bus_r <= 0; end else if(stall[3] & (!stall[4])) begin - es_to_ms1_bus_r <= 0; + dts_to_ms1_bus_r <= 0; end else if(!stall[3]) begin - es_to_ms1_bus_r <= es_to_ms1_bus; + dts_to_ms1_bus_r <= dts_to_ms1_bus; end end @@ -52,9 +52,9 @@ endmodule module mem2_stage #( - parameter ES_TO_MS_BUS_WD = 271, + parameter DT_TO_MS_BUS_WD = 271, parameter MS_TO_ES_BUS_WD = 38, - parameter MS_TO_WS_BUS_WD = 102 + parameter MS_TO_WS_BUS_WD = 172 ) ( input clk, @@ -72,14 +72,14 @@ module mem2_stage input [ 7:0] ext_int, - input [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus, - output [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus, + input [DT_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus, + output [MS_TO_ES_BUS_WD -1:0] ms2_to_es_bus, output [MS_TO_WS_BUS_WD -1:0] ms2_to_ws_bus, input [31:0] data_sram_rdata ); - reg [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus_r; + reg [DT_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus_r; reg [31:0] data_sram_rdata_r; reg [31:0] data_sram_rdata_buffer; reg [31:0] csr_rdata_buffer; @@ -132,12 +132,14 @@ module mem2_stage inst //31 :0 } = ms1_to_ms2_bus_r; - assign ms_to_es_bus = {reg_we, - dest, - ms_final_result//es_result - }; + assign ms2_to_es_bus = {reg_we, + dest, + ms_final_result//es_result + }; - assign ms2_to_ws_bus = {reg_we ,//101:101 + assign ms2_to_ws_bus = {csr_bus ,//171:108 + load_op ,//107:102 + reg_we ,//101:101 dest ,//100:96 ms_final_result ,//95 :64 ms_pc ,//63 :32 diff --git a/lacpu/rtl/mycpu/mycpu_core.v b/lacpu/rtl/mycpu/mycpu_core.v index 98ced1c..faebbc4 100644 --- a/lacpu/rtl/mycpu/mycpu_core.v +++ b/lacpu/rtl/mycpu/mycpu_core.v @@ -4,8 +4,9 @@ module mycpu_core #( parameter FS_TO_DS_BUS_WD = 34, parameter DS_TO_ES_BUS_WD = 301, - parameter ES_TO_MS_BUS_WD = 271, - parameter MS_TO_WS_BUS_WD = 102, + parameter ES_TO_DT_BUS_WD = 340, + parameter DT_TO_MS_BUS_WD = 271, + parameter MS_TO_WS_BUS_WD = 172, parameter WS_TO_RF_BUS_WD = 38, parameter MS_TO_ES_BUS_WD = 38, @@ -50,18 +51,26 @@ module mycpu_core wire [FS_TO_DS_BUS_WD -1:0] fs1_to_fs2_bus; wire [FS_TO_DS_BUS_WD -1:0] fs2_to_ds_bus; wire [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus; - wire [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus; - wire [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus; + wire [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus; + wire [DT_TO_MS_BUS_WD -1:0] dts_to_ms1_bus; + wire [DT_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus; wire [MS_TO_WS_BUS_WD -1:0] ms2_to_ws_bus; wire [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus; - wire [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus; - wire [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus; - wire [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus; + //wire [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus; + //wire [MS_TO_ES_BUS_WD -1:0] ms2_to_es_bus; + //wire [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus; wire [BR_BUS_WD -1:0] br_bus; wire [BR_BUS_WD -1:0] br_bus_real; + wire src1_is_forward; + wire src2_is_forward; + wire [31:0] src1_forward_result; + wire [31:0] src2_forward_result; + + wire stallreq_forward; + wire flush; wire stallreq_es; wire stallreq_ds; @@ -97,7 +106,7 @@ module mycpu_core assign br_target = br_bus[32] ? br_bus[31:0] : br_taken_buffer ? br_target_buffer : 32'b0; - assign br_bus_real = {br_taken, br_target}; + assign br_bus_real = {br_taken, br_target}; // TODO! if1_stage if1_stage( @@ -148,14 +157,32 @@ module mycpu_core .stallreq_es (stallreq_es ), .ds_to_es_bus (ds_to_es_bus ), - .es_to_ms1_bus (es_to_ms1_bus ), + .es_to_dts_bus (es_to_dts_bus ), - .ms1_to_es_bus (ms1_to_es_bus ), - .ms_to_es_bus (ms_to_es_bus ), - .ws_to_es_bus (ws_to_es_bus ), + .src1_is_forward (src1_is_forward ), + .src2_is_forward (src2_is_forward ), + .src1_forward_result (src1_forward_result), + .src2_forward_result (src2_forward_result), + + //.dts_to_es_bus (dts_to_es_bus ), + //.ms1_to_es_bus (ms1_to_es_bus ), + //.ms2_to_es_bus (ms2_to_es_bus ), + //.ws_to_es_bus (ws_to_es_bus ), .br_bus (br_bus ), - .br_taken_buffer (br_taken_buffer ), + .br_taken_buffer (br_taken_buffer ) + ); + + dt dt( + .clk (clk ), + .reset (reset ), + .flush (flush ), + .stall (stall ), + + .es_to_dts_bus (es_to_dts_bus ), + .dts_to_ms1_bus (dts_to_ms1_bus ), + + //.dts_to_es_bus (dts_to_es_bus ), .data_sram_en (data_sram_en ), .data_sram_we (data_sram_we ), @@ -169,10 +196,10 @@ module mycpu_core .flush (flush ), .stall (stall ), - .es_to_ms1_bus (es_to_ms1_bus ), - .ms1_to_ms2_bus (ms1_to_ms2_bus ), + .dts_to_ms1_bus (dts_to_ms1_bus ), + .ms1_to_ms2_bus (ms1_to_ms2_bus ) - .ms1_to_es_bus (ms1_to_es_bus ) + //.ms1_to_es_bus (ms1_to_es_bus ) ); @@ -189,7 +216,7 @@ module mycpu_core .ext_int (ext_int ), .ms1_to_ms2_bus (ms1_to_ms2_bus ), - .ms_to_es_bus (ms_to_es_bus ), + //.ms2_to_es_bus (ms2_to_es_bus ), .ms2_to_ws_bus (ms2_to_ws_bus ), .data_sram_rdata (data_sram_rdata ) @@ -211,13 +238,50 @@ module mycpu_core .debug_wb_rf_wdata (debug_wb_rf_wdata) ); + forward forward( + .clk (clk ), + .reset (reset), + .flush (flush), + .stall (stall), + + .rj (ds_to_es_bus[174:170] ), + .rkd (ds_to_es_bus[169:165] ), + + .es_reg_we (es_to_dts_bus[133] ), + .es_dest (es_to_dts_bus[132:128] ), + .es_result (es_to_dts_bus[127:96 ] ), + .es_ctrl ({(|es_to_dts_bus[142:137] ), (|es_to_dts_bus[195:189] )}), + + .dts_reg_we (dts_to_ms1_bus[133] ), + .dts_dest (dts_to_ms1_bus[132:128]), + .dts_result (dts_to_ms1_bus[127:96 ]), + .dts_ctrl ({(|dts_to_ms1_bus[142:137]), (|dts_to_ms1_bus[195:189])}), + + .ms1_reg_we (ms1_to_ms2_bus[133] ), + .ms1_dest (ms1_to_ms2_bus[132:128]), + .ms1_result (ms1_to_ms2_bus[127:96 ]), + .ms1_ctrl ({(|ms1_to_ms2_bus[142:137]), (|ms1_to_ms2_bus[195:189])}), + + .ms2_reg_we (ms2_to_ws_bus[101] ), + .ms2_dest (ms2_to_ws_bus[100:96] ), + .ms2_result (ms2_to_ws_bus[95 :64 ] ), + .ms2_ctrl (2'b0), + + .src1_is_forward (src1_is_forward ), + .src2_is_forward (src2_is_forward ), + .src1_forward_result (src1_forward_result ), + .src2_forward_result (src2_forward_result ), + .stallreq_forward (stallreq_forward ) + ); + + pip_ctrl pip_ctrl( .reset (reset ), .except_en (except_en ), - .stallreq_ds (stallreq_ds ), + .stallreq_ds (stallreq_forward), .stallreq_es (stallreq_es ), .stallreq_axi (stallreq_cache ), - .stallreq_cache (stallreq_cache ), + //.stallreq_cache (stallreq_cache ), .flush (flush ), .stall (stall ) ); diff --git a/lacpu/rtl/mycpu/pip_ctrl.v b/lacpu/rtl/mycpu/pip_ctrl.v index 80b9b2a..7d0166a 100644 --- a/lacpu/rtl/mycpu/pip_ctrl.v +++ b/lacpu/rtl/mycpu/pip_ctrl.v @@ -34,7 +34,7 @@ module pip_ctrl( flush = 0; stall = `StallBus'b111111; end - //id段发生暂停，此时id及之前暂? + //id段发生暂停，此时id及之前暂停 else if (stallreq_ds) begin flush = 0; stall = `StallBus'b000111; diff --git a/lacpu/rtl/mycpu/wb_stage.v b/lacpu/rtl/mycpu/wb_stage.v index 2b78e1a..5dc36ab 100644 --- a/lacpu/rtl/mycpu/wb_stage.v +++ b/lacpu/rtl/mycpu/wb_stage.v @@ -1,6 +1,6 @@ module wb_stage #( - parameter MS_TO_WS_BUS_WD = 102, + parameter MS_TO_WS_BUS_WD = 172, parameter WS_TO_RF_BUS_WD = 38, parameter WS_TO_ES_BUS_WD = 38 ) @@ -32,7 +32,7 @@ module wb_stage ms_final_result ,//95 :64 ws_pc ,//63 :32 inst //31 :0 - } = ms2_to_ws_bus_r; + } = ms2_to_ws_bus_r[101:0]; assign ws_to_rf_bus = {reg_we, dest, diff --git a/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci b/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci index 6ae03ba..dbe8b2e 100644 --- a/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci +++ b/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci @@ -98,17 +98,17 @@ 100.0 0000 0000 - 65.00000 + 84.61538 0000 0000 100.00000 BUFG 50.0 false - 65.00000 + 84.61538 0.000 50.000 - 65.000 + 85.000 0.000 1 0000 @@ -203,12 +203,12 @@ din 0000 1 - 0.65 - 0.65 - 0.65 - 0.65 - 0.65 - 0.65 + 0.85 + 0.85 + 0.85 + 0.85 + 0.85 + 0.85 dout drdy dwe @@ -246,16 +246,16 @@ false false OPTIMIZED - 13.000 + 11.000 0.000 FALSE 10.000 10.000 - 20.000 + 13.000 0.500 0.000 FALSE - 13 + 11 0.500 0.000 FALSE @@ -292,8 +292,8 @@ 2 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - _cpu_clk__65.00000______0.000______50.0______118.571_____82.897 - timer_clk__100.00000______0.000______50.0______109.471_____82.897 + _cpu_clk__84.61538______0.000______50.0______127.938_____92.672 + timer_clk__100.00000______0.000______50.0______123.670_____92.672 no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output @@ -414,18 +414,18 @@ 100.0 0.010 BUFG - 118.571 + 127.938 false - 82.897 + 92.672 50.000 - 65.000 + 85.000 0.000 1 true BUFG - 109.471 + 123.670 false - 82.897 + 92.672 50.000 100.000 0.000 @@ -525,16 +525,16 @@ No_Jitter locked OPTIMIZED - 13 + 11 0.000 false 10.000 10.000 - 20 + 13 0.500 0.000 false - 13 + 11 0.500 0.000 false @@ -712,6 +712,8 @@ + + diff --git a/lacpu/run_vivado/la32r/la32r.xpr b/lacpu/run_vivado/la32r/la32r.xpr index d702fef..f82faf3 100644 --- a/lacpu/run_vivado/la32r/la32r.xpr +++ b/lacpu/run_vivado/la32r/la32r.xpr @@ -36,13 +36,13 @@