[Add] switch to 8-stage pip & pass func test & up to 85MHz(MAX, but not pass pref test)
This commit is contained in:
63
lacpu/rtl/mycpu/dt.v
Normal file
63
lacpu/rtl/mycpu/dt.v
Normal file
@@ -0,0 +1,63 @@
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module dt
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#(
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parameter ES_TO_DT_BUS_WD = 340,
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parameter DT_TO_MS_BUS_WD = 271,
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parameter MS_TO_ES_BUS_WD = 38
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)
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(
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input clk,
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input reset,
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input flush,
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input [ 5:0] stall,
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input [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus,
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output [DT_TO_MS_BUS_WD -1:0] dts_to_ms1_bus,
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output [MS_TO_ES_BUS_WD -1:0] dts_to_es_bus,
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output data_sram_en,
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output [ 3:0] data_sram_we,
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output [31:0] data_sram_addr,
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output [31:0] data_sram_wdata
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);
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reg [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus_r;
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wire reg_we;
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wire [ 4:0] dest;
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wire [31:0] es_result;
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assign dts_to_ms1_bus = es_to_dts_bus_r[DT_TO_MS_BUS_WD -1:0];
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assign {reg_we ,
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dest ,
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es_result
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} = es_to_dts_bus_r[133:96];
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assign {data_sram_en ,
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data_sram_we ,
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data_sram_addr ,
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data_sram_wdata
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} = es_to_dts_bus_r[339:271];
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assign dts_to_es_bus = {reg_we,
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dest,
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es_result
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};
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always @(posedge clk) begin
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if (reset) begin
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es_to_dts_bus_r <= 0;
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end
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else if (flush) begin
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es_to_dts_bus_r <= 0;
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end
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else if(stall[3] & (!stall[4])) begin
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es_to_dts_bus_r <= 0;
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end
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else if(!stall[3]) begin
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es_to_dts_bus_r <= es_to_dts_bus;
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end
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end
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endmodule
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@@ -2,7 +2,7 @@ module exe_stage
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#(
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parameter BR_BUS_WD = 33,
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parameter DS_TO_ES_BUS_WD = 301,
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parameter ES_TO_MS_BUS_WD = 271,
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parameter ES_TO_DT_BUS_WD = 340,
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parameter MS_TO_ES_BUS_WD = 38,
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parameter WS_TO_ES_BUS_WD = 38
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)
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@@ -16,19 +16,24 @@ module exe_stage
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//output stallreq_es_for_cache,
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input [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus,
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output [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus,
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output [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus,
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input [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus,
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input [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus,
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input [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus,
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input src1_is_forward,
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input src2_is_forward,
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input [31:0] src1_forward_result,
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input [31:0] src2_forward_result,
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//input [MS_TO_ES_BUS_WD -1:0] dts_to_es_bus,
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//input [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus,
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//input [MS_TO_ES_BUS_WD -1:0] ms2_to_es_bus,
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//input [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus,
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output [BR_BUS_WD -1:0] br_bus,
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input br_taken_buffer,
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input br_taken_buffer
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output data_sram_en,
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output [ 3:0] data_sram_we,
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output [31:0] data_sram_addr,
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output [31:0] data_sram_wdata
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// output data_sram_en,
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// output [ 3:0] data_sram_we,
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// output [31:0] data_sram_addr,
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// output [31:0] data_sram_wdata
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);
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reg [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus_r;
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@@ -59,12 +64,15 @@ module exe_stage
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wire [31:0] es_pc;
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wire [31:0] inst;
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wire dts_reg_we;
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wire [ 4:0] dts_dest;
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wire [31:0] dts_result;
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wire ms1_reg_we;
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wire [ 4:0] ms1_dest;
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wire [31:0] ms1_result;
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wire ms_reg_we;
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wire [ 4:0] ms_dest;
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wire [31:0] ms_result;
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wire ms2_reg_we;
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wire [ 4:0] ms2_dest;
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wire [31:0] ms2_result;
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wire ws_reg_we;
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wire [ 4:0] ws_dest;
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wire [31:0] ws_result;
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@@ -92,6 +100,11 @@ module exe_stage
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wire excp_adef;
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wire excp_ale;
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wire data_sram_en;
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wire [ 3:0] data_sram_we;
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wire [31:0] data_sram_addr;
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wire [31:0] data_sram_wdata;
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assign {csr_vec_temp ,//300:237
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csr_op ,//236:230
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csr_wdata_sel ,//229:229
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@@ -117,34 +130,43 @@ module exe_stage
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inst //31 :0
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} = ds_to_es_bus_r;
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assign {ms1_reg_we,
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ms1_dest,
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ms1_result
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} = ms1_to_es_bus;
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// assign {dts_reg_we,
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// dts_dest,
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// dts_result
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// } = dts_to_es_bus;
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assign {ms_reg_we,
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ms_dest,
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ms_result
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} = ms_to_es_bus;
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// assign {ms1_reg_we,
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// ms1_dest,
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// ms1_result
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// } = ms1_to_es_bus;
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assign {ws_reg_we,
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ws_dest,
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ws_result
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} = ws_to_es_bus;
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// assign {ms2_reg_we,
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// ms2_dest,
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// ms2_result
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// } = ms2_to_es_bus;
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assign es_to_ms1_bus = {csr_vec ,//270:207
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csr_bus ,//206:143
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load_op ,//142:137
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store_op ,//136:134
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reg_we ,//133:133
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dest ,//132:128
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es_result,//127:96
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src1 ,//95 :64
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es_pc ,//63 :32
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inst //31 :0
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// assign {ws_reg_we,
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// ws_dest,
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// ws_result
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// } = ws_to_es_bus;
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assign es_to_dts_bus = {data_sram_en ,//339:339
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data_sram_we ,//338:335
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data_sram_addr ,//334:303
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data_sram_wdata ,//302:271
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csr_vec ,//270:207
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csr_bus ,//206:143
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load_op ,//142:137
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store_op ,//136:134
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reg_we ,//133:133
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dest ,//132:128
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es_result ,//127:96
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src1 ,//95 :64
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es_pc ,//63 :32
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inst //31 :0
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};
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assign br_flush = (br_taken & ~(csr_cancel|csr_cancel_reg))/* | br_taken_buffer*/; // TODO!
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assign br_flush = (br_taken & ~(csr_cancel|csr_cancel_reg)) | br_taken_buffer; // TODO!
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assign excp_adef = csr_vec[6];
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@@ -156,11 +178,11 @@ module exe_stage
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ds_to_es_bus_r <= 0;
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end
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//nop, id stall and ex not stall
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else if (stall[2]&(!stall[3])) begin
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else if (stall[2] & (!stall[3])) begin
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ds_to_es_bus_r <= 0;
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end
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//nop, id not stall and br_bus[32]
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else if (!stall[2]&br_flush) begin
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else if (!stall[2] & br_flush) begin
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ds_to_es_bus_r <= 0;
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end
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// id not stall so can go on
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@@ -169,13 +191,17 @@ module exe_stage
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end
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end
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assign src1 = ms1_reg_we & (ms1_dest == rj ) & (rj != 1'b0) ? ms1_result : // TODO!
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ms_reg_we & (ms_dest == rj ) & (rj != 1'b0) ? ms_result :
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ws_reg_we & (ws_dest == rj ) & (rj != 1'b0) ? ws_result :
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assign src1 = //dts_reg_we & (dts_dest == rj ) & (rj != 1'b0) ? dts_result : // TODO!
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//ms1_reg_we & (ms1_dest == rj ) & (rj != 1'b0) ? ms1_result : // TODO!
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//ms2_reg_we & (ms2_dest == rj ) & (rj != 1'b0) ? ms2_result :
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//ws_reg_we & (ws_dest == rj ) & (rj != 1'b0) ? ws_result :
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src1_is_forward ? src1_forward_result :
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rj_value;
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assign src2 = ms1_reg_we & (ms1_dest == rkd) & (rkd != 1'b0) ? ms1_result : // TODO!
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ms_reg_we & (ms_dest == rkd) & (rkd != 1'b0) ? ms_result :
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ws_reg_we & (ws_dest == rkd) & (rkd != 1'b0) ? ws_result :
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assign src2 = //dts_reg_we & (dts_dest == rkd) & (rkd != 1'b0) ? dts_result : // TODO!
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//ms1_reg_we & (ms1_dest == rkd) & (rkd != 1'b0) ? ms1_result : // TODO!
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//ms2_reg_we & (ms2_dest == rkd) & (rkd != 1'b0) ? ms2_result :
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//ws_reg_we & (ws_dest == rkd) & (rkd != 1'b0) ? ws_result :
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src2_is_forward ? src2_forward_result :
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rkd_value;
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assign alu_src1 = src1_is_pc ? es_pc :
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@@ -257,11 +283,12 @@ module exe_stage
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alu_result;
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assign csr_wdata = src2;
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assign csr_bus = {csr_we,
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csr_wdata_sel,
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csr_op,
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csr_addr,
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csr_wdata
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assign csr_bus = {9'b0 ,//63:55
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csr_we ,//54:54
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csr_wdata_sel ,//53:53
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csr_op ,//52:46
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csr_addr ,//45:32
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csr_wdata //31:0
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};
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assign csr_vec = {csr_vec_temp[63:8], excp_ale, csr_vec_temp[6:0]};
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109
lacpu/rtl/mycpu/forward.v
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109
lacpu/rtl/mycpu/forward.v
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@@ -0,0 +1,109 @@
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module forward
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#(
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parameter DEST_WD = 5,
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parameter RESULT_WD = 32,
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parameter CTRL_WD = 2
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)
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(
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input clk ,
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input reset,
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input flush,
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input [ 5:0] stall,
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input [ 4:0] rj,
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input [ 4:0] rkd,
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input es_reg_we ,
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input [DEST_WD -1:0] es_dest ,
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input [RESULT_WD -1:0] es_result ,
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input [CTRL_WD -1:0] es_ctrl ,
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input dts_reg_we,
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input [DEST_WD -1:0] dts_dest ,
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input [RESULT_WD -1:0] dts_result,
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input [CTRL_WD -1:0] dts_ctrl ,
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input ms1_reg_we,
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input [DEST_WD -1:0] ms1_dest ,
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input [RESULT_WD -1:0] ms1_result,
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input [CTRL_WD -1:0] ms1_ctrl ,
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input ms2_reg_we,
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input [DEST_WD -1:0] ms2_dest ,
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input [RESULT_WD -1:0] ms2_result,
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input [CTRL_WD -1:0] ms2_ctrl ,
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output reg src1_is_forward,
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output reg src2_is_forward,
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output reg [RESULT_WD -1:0] src1_forward_result,
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output reg [RESULT_WD -1:0] src2_forward_result,
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output stallreq_forward
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);
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wire src1_is_es_result;
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wire src1_is_dts_result;
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wire src1_is_ms1_result;
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wire src1_is_ms2_result;
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wire src2_is_es_result;
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wire src2_is_dts_result;
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wire src2_is_ms1_result;
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wire src2_is_ms2_result;
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wire src1_is_forward_w;
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wire src2_is_forward_w;
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wire [RESULT_WD -1:0] src1_forward_result_w;
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wire [RESULT_WD -1:0] src2_forward_result_w;
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assign src1_is_es_result = es_reg_we & (rj == es_dest ) & (rj != 0);
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assign src1_is_dts_result = dts_reg_we & (rj == dts_dest) & (rj != 0);
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assign src1_is_ms1_result = ms1_reg_we & (rj == ms1_dest) & (rj != 0);
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assign src1_is_ms2_result = ms2_reg_we & (rj == ms2_dest) & (rj != 0);
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assign src2_is_es_result = es_reg_we & (rkd == es_dest ) & (rkd != 0);
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assign src2_is_dts_result = dts_reg_we & (rkd == dts_dest) & (rkd != 0);
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assign src2_is_ms1_result = ms1_reg_we & (rkd == ms1_dest) & (rkd != 0);
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assign src2_is_ms2_result = ms2_reg_we & (rkd == ms2_dest) & (rkd != 0);
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assign src1_is_forward_w = src1_is_es_result | src1_is_dts_result | src1_is_ms1_result | src1_is_ms2_result;
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assign src2_is_forward_w = src2_is_es_result | src2_is_dts_result | src2_is_ms1_result | src2_is_ms2_result;
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assign src1_forward_result_w = src1_is_es_result ? es_result :
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src1_is_dts_result ? dts_result :
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src1_is_ms1_result ? ms1_result :
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src1_is_ms2_result ? ms2_result :
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32'b0;
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assign src2_forward_result_w = src2_is_es_result ? es_result :
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src2_is_dts_result ? dts_result :
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src2_is_ms1_result ? ms1_result :
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src2_is_ms2_result ? ms2_result :
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32'b0;
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assign stallreq_forward = ((|es_ctrl ) & (src1_is_es_result | src2_is_es_result ))
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| ((|dts_ctrl) & (src1_is_dts_result | src2_is_dts_result))
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| ((|ms1_ctrl) & (src1_is_ms1_result | src2_is_ms1_result));
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//| ((|ms2_ctrl) & (src1_is_ms2_result | src2_is_ms2_result));
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always @(posedge clk) begin
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if (reset) begin
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src1_is_forward <= 0;
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src2_is_forward <= 0;
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src1_forward_result <= 0;
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src2_forward_result <= 0;
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end
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else if (stall[2] & (!stall[3])) begin
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src1_is_forward <= 0;
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src2_is_forward <= 0;
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src1_forward_result <= 0;
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src2_forward_result <= 0;
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end
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else if (!stall[2]) begin
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src1_is_forward <= src1_is_forward_w;
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src2_is_forward <= src2_is_forward_w;
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src1_forward_result <= src1_forward_result_w;
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src2_forward_result <= src2_forward_result_w;
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end
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end
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endmodule
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@@ -1,6 +1,6 @@
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module mem1_stage
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#(
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parameter ES_TO_MS_BUS_WD = 271,
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parameter DT_TO_MS_BUS_WD = 271,
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parameter MS_TO_ES_BUS_WD = 38
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)
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(
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@@ -9,22 +9,22 @@ module mem1_stage
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input flush,
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input [ 5:0] stall,
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input [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus,
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output [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus,
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input [DT_TO_MS_BUS_WD -1:0] dts_to_ms1_bus,
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output [DT_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus,
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output [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus
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);
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reg [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus_r;
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reg [DT_TO_MS_BUS_WD -1:0] dts_to_ms1_bus_r;
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wire reg_we;
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wire [ 4:0] dest;
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wire [31:0] es_result;
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assign ms1_to_ms2_bus = es_to_ms1_bus_r;
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assign ms1_to_ms2_bus = dts_to_ms1_bus_r;
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assign reg_we = es_to_ms1_bus_r[133:133];
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assign dest = es_to_ms1_bus_r[132:128];
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assign es_result = es_to_ms1_bus_r[127:96];
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assign reg_we = dts_to_ms1_bus_r[133:133];
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assign dest = dts_to_ms1_bus_r[132:128];
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assign es_result = dts_to_ms1_bus_r[127:96];
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|
||||
assign ms1_to_es_bus = {reg_we,
|
||||
dest,
|
||||
@@ -33,16 +33,16 @@ assign ms1_to_es_bus = {reg_we,
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
es_to_ms1_bus_r <= 0;
|
||||
dts_to_ms1_bus_r <= 0;
|
||||
end
|
||||
else if (flush) begin
|
||||
es_to_ms1_bus_r <= 0;
|
||||
dts_to_ms1_bus_r <= 0;
|
||||
end
|
||||
else if(stall[3] & (!stall[4])) begin
|
||||
es_to_ms1_bus_r <= 0;
|
||||
dts_to_ms1_bus_r <= 0;
|
||||
end
|
||||
else if(!stall[3]) begin
|
||||
es_to_ms1_bus_r <= es_to_ms1_bus;
|
||||
dts_to_ms1_bus_r <= dts_to_ms1_bus;
|
||||
end
|
||||
end
|
||||
|
||||
@@ -52,9 +52,9 @@ endmodule
|
||||
|
||||
module mem2_stage
|
||||
#(
|
||||
parameter ES_TO_MS_BUS_WD = 271,
|
||||
parameter DT_TO_MS_BUS_WD = 271,
|
||||
parameter MS_TO_ES_BUS_WD = 38,
|
||||
parameter MS_TO_WS_BUS_WD = 102
|
||||
parameter MS_TO_WS_BUS_WD = 172
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
@@ -72,14 +72,14 @@ module mem2_stage
|
||||
|
||||
input [ 7:0] ext_int,
|
||||
|
||||
input [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus,
|
||||
output [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus,
|
||||
input [DT_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus,
|
||||
output [MS_TO_ES_BUS_WD -1:0] ms2_to_es_bus,
|
||||
output [MS_TO_WS_BUS_WD -1:0] ms2_to_ws_bus,
|
||||
|
||||
input [31:0] data_sram_rdata
|
||||
);
|
||||
|
||||
reg [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus_r;
|
||||
reg [DT_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus_r;
|
||||
reg [31:0] data_sram_rdata_r;
|
||||
reg [31:0] data_sram_rdata_buffer;
|
||||
reg [31:0] csr_rdata_buffer;
|
||||
@@ -132,12 +132,14 @@ module mem2_stage
|
||||
inst //31 :0
|
||||
} = ms1_to_ms2_bus_r;
|
||||
|
||||
assign ms_to_es_bus = {reg_we,
|
||||
dest,
|
||||
ms_final_result//es_result
|
||||
};
|
||||
assign ms2_to_es_bus = {reg_we,
|
||||
dest,
|
||||
ms_final_result//es_result
|
||||
};
|
||||
|
||||
assign ms2_to_ws_bus = {reg_we ,//101:101
|
||||
assign ms2_to_ws_bus = {csr_bus ,//171:108
|
||||
load_op ,//107:102
|
||||
reg_we ,//101:101
|
||||
dest ,//100:96
|
||||
ms_final_result ,//95 :64
|
||||
ms_pc ,//63 :32
|
||||
|
||||
@@ -4,8 +4,9 @@ module mycpu_core
|
||||
#(
|
||||
parameter FS_TO_DS_BUS_WD = 34,
|
||||
parameter DS_TO_ES_BUS_WD = 301,
|
||||
parameter ES_TO_MS_BUS_WD = 271,
|
||||
parameter MS_TO_WS_BUS_WD = 102,
|
||||
parameter ES_TO_DT_BUS_WD = 340,
|
||||
parameter DT_TO_MS_BUS_WD = 271,
|
||||
parameter MS_TO_WS_BUS_WD = 172,
|
||||
parameter WS_TO_RF_BUS_WD = 38,
|
||||
|
||||
parameter MS_TO_ES_BUS_WD = 38,
|
||||
@@ -50,18 +51,26 @@ module mycpu_core
|
||||
wire [FS_TO_DS_BUS_WD -1:0] fs1_to_fs2_bus;
|
||||
wire [FS_TO_DS_BUS_WD -1:0] fs2_to_ds_bus;
|
||||
wire [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
|
||||
wire [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus;
|
||||
wire [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus;
|
||||
wire [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus;
|
||||
wire [DT_TO_MS_BUS_WD -1:0] dts_to_ms1_bus;
|
||||
wire [DT_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus;
|
||||
wire [MS_TO_WS_BUS_WD -1:0] ms2_to_ws_bus;
|
||||
wire [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
|
||||
|
||||
wire [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus;
|
||||
wire [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
|
||||
wire [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
|
||||
//wire [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus;
|
||||
//wire [MS_TO_ES_BUS_WD -1:0] ms2_to_es_bus;
|
||||
//wire [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
|
||||
|
||||
wire [BR_BUS_WD -1:0] br_bus;
|
||||
wire [BR_BUS_WD -1:0] br_bus_real;
|
||||
|
||||
wire src1_is_forward;
|
||||
wire src2_is_forward;
|
||||
wire [31:0] src1_forward_result;
|
||||
wire [31:0] src2_forward_result;
|
||||
|
||||
wire stallreq_forward;
|
||||
|
||||
wire flush;
|
||||
wire stallreq_es;
|
||||
wire stallreq_ds;
|
||||
@@ -97,7 +106,7 @@ module mycpu_core
|
||||
assign br_target = br_bus[32] ? br_bus[31:0] :
|
||||
br_taken_buffer ? br_target_buffer :
|
||||
32'b0;
|
||||
assign br_bus_real = {br_taken, br_target};
|
||||
assign br_bus_real = {br_taken, br_target}; // TODO!
|
||||
|
||||
|
||||
if1_stage if1_stage(
|
||||
@@ -148,14 +157,32 @@ module mycpu_core
|
||||
.stallreq_es (stallreq_es ),
|
||||
|
||||
.ds_to_es_bus (ds_to_es_bus ),
|
||||
.es_to_ms1_bus (es_to_ms1_bus ),
|
||||
.es_to_dts_bus (es_to_dts_bus ),
|
||||
|
||||
.ms1_to_es_bus (ms1_to_es_bus ),
|
||||
.ms_to_es_bus (ms_to_es_bus ),
|
||||
.ws_to_es_bus (ws_to_es_bus ),
|
||||
.src1_is_forward (src1_is_forward ),
|
||||
.src2_is_forward (src2_is_forward ),
|
||||
.src1_forward_result (src1_forward_result),
|
||||
.src2_forward_result (src2_forward_result),
|
||||
|
||||
//.dts_to_es_bus (dts_to_es_bus ),
|
||||
//.ms1_to_es_bus (ms1_to_es_bus ),
|
||||
//.ms2_to_es_bus (ms2_to_es_bus ),
|
||||
//.ws_to_es_bus (ws_to_es_bus ),
|
||||
|
||||
.br_bus (br_bus ),
|
||||
.br_taken_buffer (br_taken_buffer ),
|
||||
.br_taken_buffer (br_taken_buffer )
|
||||
);
|
||||
|
||||
dt dt(
|
||||
.clk (clk ),
|
||||
.reset (reset ),
|
||||
.flush (flush ),
|
||||
.stall (stall ),
|
||||
|
||||
.es_to_dts_bus (es_to_dts_bus ),
|
||||
.dts_to_ms1_bus (dts_to_ms1_bus ),
|
||||
|
||||
//.dts_to_es_bus (dts_to_es_bus ),
|
||||
|
||||
.data_sram_en (data_sram_en ),
|
||||
.data_sram_we (data_sram_we ),
|
||||
@@ -169,10 +196,10 @@ module mycpu_core
|
||||
.flush (flush ),
|
||||
.stall (stall ),
|
||||
|
||||
.es_to_ms1_bus (es_to_ms1_bus ),
|
||||
.ms1_to_ms2_bus (ms1_to_ms2_bus ),
|
||||
.dts_to_ms1_bus (dts_to_ms1_bus ),
|
||||
.ms1_to_ms2_bus (ms1_to_ms2_bus )
|
||||
|
||||
.ms1_to_es_bus (ms1_to_es_bus )
|
||||
//.ms1_to_es_bus (ms1_to_es_bus )
|
||||
);
|
||||
|
||||
|
||||
@@ -189,7 +216,7 @@ module mycpu_core
|
||||
.ext_int (ext_int ),
|
||||
|
||||
.ms1_to_ms2_bus (ms1_to_ms2_bus ),
|
||||
.ms_to_es_bus (ms_to_es_bus ),
|
||||
//.ms2_to_es_bus (ms2_to_es_bus ),
|
||||
.ms2_to_ws_bus (ms2_to_ws_bus ),
|
||||
|
||||
.data_sram_rdata (data_sram_rdata )
|
||||
@@ -211,13 +238,50 @@ module mycpu_core
|
||||
.debug_wb_rf_wdata (debug_wb_rf_wdata)
|
||||
);
|
||||
|
||||
forward forward(
|
||||
.clk (clk ),
|
||||
.reset (reset),
|
||||
.flush (flush),
|
||||
.stall (stall),
|
||||
|
||||
.rj (ds_to_es_bus[174:170] ),
|
||||
.rkd (ds_to_es_bus[169:165] ),
|
||||
|
||||
.es_reg_we (es_to_dts_bus[133] ),
|
||||
.es_dest (es_to_dts_bus[132:128] ),
|
||||
.es_result (es_to_dts_bus[127:96 ] ),
|
||||
.es_ctrl ({(|es_to_dts_bus[142:137] ), (|es_to_dts_bus[195:189] )}),
|
||||
|
||||
.dts_reg_we (dts_to_ms1_bus[133] ),
|
||||
.dts_dest (dts_to_ms1_bus[132:128]),
|
||||
.dts_result (dts_to_ms1_bus[127:96 ]),
|
||||
.dts_ctrl ({(|dts_to_ms1_bus[142:137]), (|dts_to_ms1_bus[195:189])}),
|
||||
|
||||
.ms1_reg_we (ms1_to_ms2_bus[133] ),
|
||||
.ms1_dest (ms1_to_ms2_bus[132:128]),
|
||||
.ms1_result (ms1_to_ms2_bus[127:96 ]),
|
||||
.ms1_ctrl ({(|ms1_to_ms2_bus[142:137]), (|ms1_to_ms2_bus[195:189])}),
|
||||
|
||||
.ms2_reg_we (ms2_to_ws_bus[101] ),
|
||||
.ms2_dest (ms2_to_ws_bus[100:96] ),
|
||||
.ms2_result (ms2_to_ws_bus[95 :64 ] ),
|
||||
.ms2_ctrl (2'b0),
|
||||
|
||||
.src1_is_forward (src1_is_forward ),
|
||||
.src2_is_forward (src2_is_forward ),
|
||||
.src1_forward_result (src1_forward_result ),
|
||||
.src2_forward_result (src2_forward_result ),
|
||||
.stallreq_forward (stallreq_forward )
|
||||
);
|
||||
|
||||
|
||||
pip_ctrl pip_ctrl(
|
||||
.reset (reset ),
|
||||
.except_en (except_en ),
|
||||
.stallreq_ds (stallreq_ds ),
|
||||
.stallreq_ds (stallreq_forward),
|
||||
.stallreq_es (stallreq_es ),
|
||||
.stallreq_axi (stallreq_cache ),
|
||||
.stallreq_cache (stallreq_cache ),
|
||||
//.stallreq_cache (stallreq_cache ),
|
||||
.flush (flush ),
|
||||
.stall (stall )
|
||||
);
|
||||
|
||||
@@ -34,7 +34,7 @@ module pip_ctrl(
|
||||
flush = 0;
|
||||
stall = `StallBus'b111111;
|
||||
end
|
||||
//id段å<EFBFBD>‘生暂å<EFBFBD>œï¼Œæ¤æ—¶idå<EFBFBD>Šä¹‹å‰<EFBFBD>æš‚å<EFBFBD>?
|
||||
//id段发生暂停，此时id及之前暂停
|
||||
else if (stallreq_ds) begin
|
||||
flush = 0;
|
||||
stall = `StallBus'b000111;
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
module wb_stage
|
||||
#(
|
||||
parameter MS_TO_WS_BUS_WD = 102,
|
||||
parameter MS_TO_WS_BUS_WD = 172,
|
||||
parameter WS_TO_RF_BUS_WD = 38,
|
||||
parameter WS_TO_ES_BUS_WD = 38
|
||||
)
|
||||
@@ -32,7 +32,7 @@ module wb_stage
|
||||
ms_final_result ,//95 :64
|
||||
ws_pc ,//63 :32
|
||||
inst //31 :0
|
||||
} = ms2_to_ws_bus_r;
|
||||
} = ms2_to_ws_bus_r[101:0];
|
||||
|
||||
assign ws_to_rf_bus = {reg_we,
|
||||
dest,
|
||||
|
||||
@@ -98,17 +98,17 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">65.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">84.61538</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">100.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">65.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">84.61538</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">65.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">85.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
|
||||
@@ -203,12 +203,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.65</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.65</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.65</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.65</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.65</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.65</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.85</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.85</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.85</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.85</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.85</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.85</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
|
||||
@@ -246,16 +246,16 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">13.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">11.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">20.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">13.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
@@ -292,8 +292,8 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__65.00000______0.000______50.0______118.571_____82.897</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">timer_clk__100.00000______0.000______50.0______109.471_____82.897</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__84.61538______0.000______50.0______127.938_____92.672</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">timer_clk__100.00000______0.000______50.0______123.670_____92.672</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
|
||||
@@ -414,18 +414,18 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">118.571</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">127.938</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">82.897</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">92.672</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">65.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">85.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">109.471</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">123.670</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">82.897</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">92.672</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
@@ -525,16 +525,16 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
@@ -712,6 +712,8 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT2_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FEEDBACK_SOURCE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_COMPENSATION" xilinx:valueSource="user"/>
|
||||
|
||||
Reference in New Issue
Block a user