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[Modified] Change branch site, without stall (need 1 stall)

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包焕垲
2023-06-12 15:36:00 +08:00
parent f592606196
commit 8d1aa17074
10 changed files with 93 additions and 144 deletions
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13
lacpu/rtl/cpu/alu.v
View File

@@ -2,12 +2,7 @@ module alu(
input [14:0] alu_op ,
input [31:0] alu_src1 ,
input [31:0] alu_src2 ,
output [31:0] alu_result ,
output Carry ,
output Sign ,
output Overflow ,
output Zero
output [31:0] alu_result
);
wire op_add;
@@ -117,11 +112,5 @@ module alu(
| ({32{op_sll }} & sll_result)
| ({32{op_srl|op_sra }} & sr_result)
| ({32{op_mul|op_mulh|op_mulhu}} & mul_result);
assign Carry = op_sub ^ adder_cout;
assign Sign = alu_result[31];
assign Overflow = (op_add|op_sub) ? ( adder_a[31] & adder_b[31] & adder_cout)
| (~adder_a[31] & ~adder_b[31] & ~adder_cout)
: 1'b0;
assign Zero = (alu_result == 32'b0);
endmodule

55
lacpu/rtl/cpu/exe_stage.v
View File

@@ -45,7 +45,6 @@ module exe_stage(
wire es_mem_we;
wire [ 4:0] es_load_op;
wire [ 2:0] es_store_op;
wire [ 8:0] es_branch_op;
wire [ 4:0] es_dest;
wire [31:0] es_imm;
wire [31:0] es_pc;
@@ -59,16 +58,15 @@ module exe_stage(
wire es_src2_is_ms_dest;
wire es_data_is_rf_wdata;
assign {es_alu_op , //173:155
es_src1_is_pc , //154:154
es_src2_is_imm , //153:153
es_src2_is_4 , //152:152
es_mem_to_reg , //151:151
es_reg_we , //150:150
es_mem_we , //149:149
es_load_op , //148:142
es_store_op , //141:141
es_branch_op , //141:133
assign {es_alu_op , //159:141
es_src1_is_pc , //140:140
es_src2_is_imm , //139:139
es_src2_is_4 , //138:138
es_mem_to_reg , //137:137
es_reg_we , //136:136
es_mem_we , //135:135
es_load_op , //134:134
es_store_op , //133:133
es_dest , //132:128
es_imm , //127:96
es_rf_rdata1 , //95 :64
@@ -86,8 +84,6 @@ module exe_stage(
assign ms_alu_result = ms_to_ds_bus;
assign ws_rf_wdata = ws_to_ds_bus;
wire [31:0] br_target;
wire [31:0] es_alu_src1 ;
wire [31:0] es_alu_src2 ;
wire [31:0] es_alu_result;
@@ -103,19 +99,13 @@ module exe_stage(
wire [ 1:0] div_op;
wire div_stall;
assign es_to_ms_bus = {div_op , //122:121
br_target , //120:89
es_branch_op , //88 :80
es_Carry , //79 :79
es_Sign , //78 :78
es_Overflow , //77 :77
es_Zero , //76 :76
es_load_op , //75 :71
es_mem_to_reg , //70 :70
es_reg_we , //69 :69
es_dest , //68 :64
es_alu_result , //63 :32
es_pc //31 :0
assign es_to_ms_bus = {div_op , //77:76
es_load_op , //75:71
es_mem_to_reg , //70:70
es_reg_we , //69:69
es_dest , //68:64
es_alu_result , //63:32
es_pc //31:0
};
assign es_to_fw_bus = {es_rf_rdata2 ,
@@ -163,7 +153,7 @@ module exe_stage(
assign es_div_enable = (div_op[0] | div_op[1]) & es_valid;
assign es_div_sign = es_inst_divw | es_inst_modw;
assign es_div_sign = es_inst_divw | es_inst_modw;
assign div_stall = es_div_enable & ~div_complete;
@@ -171,12 +161,7 @@ module exe_stage(
.alu_op (es_alu_op[14:0]),
.alu_src1 (es_alu_src1 ),
.alu_src2 (es_alu_src2 ),
.alu_result (es_alu_result),
.Carry (es_Carry ),
.Sign (es_Sign ),
.Overflow (es_Overflow ),
.Zero (es_Zero )
.alu_result (es_alu_result)
);
assign data_sram_en = 1'b1;
@@ -196,8 +181,4 @@ module exe_stage(
es_store_op[2] ? es_rf_rdata2 :
32'b0;
assign br_target = (|es_branch_op[7:0]) ? (es_alu_result ) :
( es_branch_op[8] ) ? (es_rf_rdata1 + es_imm) :
0;
endmodule

67
lacpu/rtl/cpu/id_stage.v
View File

@@ -13,10 +13,12 @@ module id_stage(
//to es
output ds_to_es_valid,
output [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus ,
//to fs
//to rf
input [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus ,
//to fw
output [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus
output [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus ,
//to fs
output [`BR_BUS_WD -1:0] br_bus
);
reg ds_valid ;
@@ -48,7 +50,6 @@ module id_stage(
wire mem_we;
wire [ 4:0] load_op;
wire [ 2:0] store_op;
wire [ 8:0] branch_op;
wire [ 4:0] dest;
wire [31:0] imm;
@@ -109,8 +110,6 @@ module id_stage(
wire inst_divwu;
wire inst_modwu;
wire dst_is_r1;
wire [ 4:0] rf_raddr1;
@@ -118,16 +117,21 @@ module id_stage(
wire [ 4:0] rf_raddr2;
wire [31:0] rf_rdata2;
assign ds_to_es_bus = {alu_op , //173:155
src1_is_pc , //154:154
src2_is_imm , //153:153
src2_is_4 , //152:152
mem_to_reg , //151:151
reg_we , //150:150
mem_we , //149:149
load_op , //148:142
store_op , //141:141
branch_op , //141:133
wire rj_eq_rd;
wire rj_lt_rd_unsign;
wire rj_lt_rd_sign;
wire br_taken;
wire [31:0] br_target;
assign ds_to_es_bus = {alu_op , //159:141
src1_is_pc , //140:140
src2_is_imm , //139:139
src2_is_4 , //138:138
mem_to_reg , //137:137
reg_we , //136:136
mem_we , //135:135
load_op , //134:134
store_op , //133:133
dest , //132:128
imm , //127:96
rf_rdata1 , //95 :64
@@ -135,10 +139,12 @@ module id_stage(
ds_pc //31 :0
};
assign ds_to_fw_bus = {rf_raddr1 , rf_raddr2};
assign ds_to_fw_bus = {rf_raddr1 ,
rf_raddr2
};
assign ds_ready_go = 1'b1;
assign ds_allowin = !ds_valid || ds_ready_go && es_allowin;
assign ds_allowin = (!ds_valid || ds_ready_go && es_allowin);
assign ds_to_es_valid = ds_valid && ds_ready_go;
always @(posedge clk) begin
@@ -215,7 +221,7 @@ module id_stage(
assign inst_bltu = (op[21:19] == 3'b011 ) & op6_d[3'b010];
assign inst_bgeu = (op[21:19] == 3'b011 ) & op6_d[3'b011];
assign alu_op[ 0] = inst_addw | inst_addiw | inst_pcaddu12i | inst_ldb | inst_ldh | inst_ldbu | inst_ldhu | inst_ldw | inst_stb | inst_sth | inst_stw | inst_bl | inst_jirl | inst_b;
assign alu_op[ 0] = inst_addw | inst_addiw | inst_pcaddu12i | inst_ldb | inst_ldh | inst_ldbu | inst_ldhu | inst_ldw | inst_stb | inst_sth | inst_stw;
assign alu_op[ 1] = inst_subw;
assign alu_op[ 2] = inst_slt | inst_slti;
assign alu_op[ 3] = inst_sltu | inst_sltui;
@@ -242,9 +248,9 @@ module id_stage(
| {32{inst_slliw | inst_srliw | inst_sraiw}} & { 27'b0 , rk}
| {32{inst_b | inst_bl}} & {{4{ds_inst[9]}}, ds_inst[9:0], ds_inst[25:10], 2'b0};
assign src1_is_pc = inst_bl | inst_jirl | inst_pcaddu12i | inst_b;
assign src2_is_4 = inst_bl | inst_jirl;
assign src2_is_imm = inst_addiw | inst_lu12iw | inst_pcaddu12i | inst_andi | inst_ori | inst_xori | inst_slliw | inst_srliw | inst_sraiw | inst_ldb | inst_ldh | inst_ldw | inst_ldbu | inst_ldhu | inst_stb | inst_sth | inst_stw | inst_mulhwu | inst_divwu | inst_modwu | inst_b | inst_beq | inst_bne | inst_bge | inst_bgeu | inst_blt | inst_bltu;
assign src1_is_pc = inst_bl | inst_jirl | inst_pcaddu12i | inst_b;
assign src2_is_4 = inst_bl | inst_jirl;
assign src2_is_imm = inst_addiw | inst_lu12iw | inst_pcaddu12i | inst_andi | inst_ori | inst_xori | inst_slliw | inst_srliw | inst_sraiw | inst_ldb | inst_ldh | inst_ldw | inst_ldbu | inst_ldhu | inst_stb | inst_sth | inst_stw | inst_mulhwu | inst_divwu | inst_modwu | inst_b | inst_beq | inst_bne | inst_bge | inst_bgeu | inst_blt | inst_bltu;
assign dst_is_r1 = inst_bl;
assign reg_we = ~(inst_b | inst_beq | inst_bne | inst_bge | inst_bgeu | inst_blt | inst_bltu | inst_stw | inst_sth | inst_stb);
@@ -252,7 +258,6 @@ module id_stage(
assign mem_to_reg = inst_ldw | inst_ldh | inst_ldb | inst_ldhu | inst_ldbu;
assign load_op = {inst_ldhu, inst_ldbu, inst_ldw, inst_ldh, inst_ldb};
assign store_op = {inst_stw , inst_sth , inst_stb};
assign branch_op = {inst_jirl, inst_bl , inst_b , inst_bgeu, inst_bltu, inst_bge, inst_blt, inst_bne, inst_beq};
assign dest = dst_is_r1 ? 5'd1 :
rd;
@@ -270,4 +275,22 @@ module id_stage(
.wdata (rf_wdata )
);
assign rj_eq_rd = (rf_rdata1 == rf_rdata2);
assign rj_lt_rd_unsign = (rf_rdata1 < rf_rdata2);
assign rj_lt_rd_sign = (rf_rdata1[31] && ~rf_rdata2[31]) ? 1'b1 :
(~rf_rdata1[31] && rf_rdata2[31]) ? 1'b0 : rj_lt_rd_unsign;
assign br_taken = ( inst_beq && rj_eq_rd
|| inst_bne && !rj_eq_rd
|| inst_blt && rj_lt_rd_sign
|| inst_bge && !rj_lt_rd_sign
|| inst_bltu && rj_lt_rd_unsign
|| inst_bgeu && !rj_lt_rd_unsign
|| inst_jirl
|| inst_bl
|| inst_b
);
assign br_target = ({32{inst_beq || inst_bne || inst_bl || inst_b || inst_blt || inst_bge || inst_bltu || inst_bgeu}} & (ds_pc + imm))
| ({32{inst_jirl}} & (rf_rdata1 + imm)) ;
assign br_bus = {br_taken, br_target};
endmodule

4
lacpu/rtl/cpu/if_stage.v
View File

@@ -29,12 +29,12 @@ module if_stage(
wire br_taken;
wire [ 31:0] br_target;
assign {br_taken,br_target} = br_bus;
assign {br_taken, br_target} = br_bus;
wire [31:0] fs_inst;
reg [31:0] fs_pc;
assign fs_to_ds_bus = {fs_inst ,
fs_pc };
fs_pc };
// pre-IF stage
assign to_fs_valid = ~reset;

42
lacpu/rtl/cpu/mem_stage.v
View File

@@ -12,8 +12,6 @@ module mem_stage(
//to ws
output ms_to_ws_valid ,
output [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus ,
//to fs
output [`BR_BUS_WD -1:0] br_bus ,
//from data-sram
input [31 :0] data_sram_rdata,
//to fw
@@ -29,8 +27,6 @@ module mem_stage(
wire ms_ready_go;
reg [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus_r;
wire [31:0] br_target;
wire [ 8:0] ms_branch_op;
wire [ 4:0] ms_load_op;
wire [ 2:0] ms_store_op;
wire ms_mem_to_reg;
@@ -39,32 +35,19 @@ module mem_stage(
wire [31:0] ms_alu_result;
wire [31:0] ms_pc;
wire [ 1:0] ms_div_op;
wire ms_Carry ;
wire ms_Sign ;
wire ms_Overflow ;
wire ms_Zero ;
assign {ms_div_op , //122:121
br_target , //120:89
ms_branch_op , //88 :80
ms_Carry , //79 :79
ms_Sign , //78 :78
ms_Overflow , //77 :77
ms_Zero , //76 :76
ms_load_op , //75 :71
ms_mem_to_reg , //70 :70
ms_reg_we , //69 :69
ms_dest , //68 :64
ms_alu_result , //63 :32
ms_pc //31 :0
assign {ms_div_op , //77:76
ms_load_op , //75:71
ms_mem_to_reg , //70:70
ms_reg_we , //69:69
ms_dest , //68:64
ms_alu_result , //63:32
ms_pc //31:0
} = es_to_ms_bus_r;
wire br_taken;
wire [31:0] mem_result;
wire [31:0] ms_final_result;
assign br_bus = {br_taken, br_target};
assign ms_to_ws_bus = {ms_reg_we , //69:69
ms_dest , //68:64
@@ -109,15 +92,4 @@ module mem_stage(
ms_div_op[1] ? mod_result :
ms_alu_result;
assign br_taken = ( ms_branch_op[0] & ms_Zero
| ms_branch_op[1] & !ms_Zero
| ms_branch_op[2] & (ms_Sign != ms_Overflow)
| ms_branch_op[3] & (ms_Zero | (ms_Sign == ms_Overflow))
| ms_branch_op[4] & ms_Carry
| ms_branch_op[5] & (ms_Zero | ~ms_Carry )
| ms_branch_op[6]
| ms_branch_op[7]
| ms_branch_op[8]);
endmodule

8
lacpu/rtl/cpu/mycpu.vh
View File

@@ -3,8 +3,8 @@
`define BR_BUS_WD 33
`define FS_TO_DS_BUS_WD 64
`define DS_TO_ES_BUS_WD 174
`define ES_TO_MS_BUS_WD 123
`define DS_TO_ES_BUS_WD 160
`define ES_TO_MS_BUS_WD 78
`define MS_TO_WS_BUS_WD 70
`define WS_TO_RF_BUS_WD 38
@@ -12,10 +12,6 @@
`define ES_TO_FW_BUS_WD 12
`define MS_TO_FW_BUS_WD 6
`define FW_TO_ES_BUS_WD 5
`define MS_TO_ES_BUS_WD 32
`define WS_TO_ES_BUS_WD 32
`define DS_TO_LU_BUS_WD 10
`define ES_TO_LU_BUS_WD 10
`endif

6
lacpu/rtl/cpu/mycpu_top.v
View File

@@ -88,7 +88,9 @@ module mycpu_top(
//to rf: for write back
.ws_to_rf_bus (ws_to_rf_bus ),
//to fw
.ds_to_fw_bus (ds_to_fw_bus )
.ds_to_fw_bus (ds_to_fw_bus ),
//to fs
.br_bus (br_bus )
);
// EXE stage
exe_stage exe_stage(
@@ -149,8 +151,6 @@ module mycpu_top(
//to ws
.ms_to_ws_valid (ms_to_ws_valid ),
.ms_to_ws_bus (ms_to_ws_bus ),
//to fs
.br_bus (br_bus ),
//from data-sram
.data_sram_rdata(data_sram_rdata),
//to fw

8
lacpu/rtl/cpu/tools.v
View File

@@ -12,10 +12,10 @@ module decoder_5_32(
endmodule
module decoder_3_8(
input [2:0] in,
output [7:0] out
);
module decoder_3_8(
input [2:0] in,
output [7:0] out
);
genvar i;
generate for (i=0; i<8; i=i+1) begin : gen_for_dec_3_8

2
lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe
View File

@@ -1,2 +1,2 @@
memory_initialization_radix=16;
memory_initialization_vector=28800401 02800822;
memory_initialization_vector=50000000 28800401 02800822;

32
lacpu/run_vivado/la32r/la32r.xpr
View File

@@ -29,20 +29,20 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="WTXSimLaunchSim" Val="22"/>
<Option Name="WTXSimLaunchSim" Val="29"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="12"/>
<Option Name="WTModelSimExportSim" Val="12"/>
<Option Name="WTQuestaExportSim" Val="12"/>
<Option Name="WTIesExportSim" Val="12"/>
<Option Name="WTVcsExportSim" Val="12"/>
<Option Name="WTRivieraExportSim" Val="12"/>
<Option Name="WTActivehdlExportSim" Val="12"/>
<Option Name="WTXSimExportSim" Val="16"/>
<Option Name="WTModelSimExportSim" Val="16"/>
<Option Name="WTQuestaExportSim" Val="16"/>
<Option Name="WTIesExportSim" Val="16"/>
<Option Name="WTVcsExportSim" Val="16"/>
<Option Name="WTRivieraExportSim" Val="16"/>
<Option Name="WTActivehdlExportSim" Val="16"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -138,14 +138,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/cpu/loaduse.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/xilinx_ip/inst_ram/inst_ram.coe">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -258,9 +250,7 @@
<Runs Version="1" Minor="11">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -290,9 +280,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>