197 lines
6.0 KiB
Verilog
197 lines
6.0 KiB
Verilog
`include "mycpu.vh"
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module mycpu_top(
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input clk,
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input resetn,
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// inst sram interface
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output inst_sram_en,
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output [ 3:0] inst_sram_we,
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output [31:0] inst_sram_addr,
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output [31:0] inst_sram_wdata,
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input [31:0] inst_sram_rdata,
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// data sram interface
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output data_sram_en,
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output [ 3:0] data_sram_we,
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output [31:0] data_sram_addr,
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output [31:0] data_sram_wdata,
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input [31:0] data_sram_rdata,
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// trace debug interface
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output [31:0] debug_wb_pc,
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output [ 3:0] debug_wb_rf_we,
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output [ 4:0] debug_wb_rf_wnum,
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output [31:0] debug_wb_rf_wdata
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);
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reg reset;
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always @(posedge clk) reset <= ~resetn;
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wire ds_allowin;
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wire es_allowin;
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wire ms_allowin;
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wire ws_allowin;
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wire fs_to_ds_valid;
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wire ds_to_es_valid;
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wire es_to_ms_valid;
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wire ms_to_ws_valid;
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wire [`FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus;
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wire [`DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
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wire [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus;
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wire [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;
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wire [`WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
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wire [`BR_BUS_WD -1:0] br_bus;
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wire [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus;
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wire [`ES_TO_FW_BUS_WD -1:0] es_to_fw_bus;
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wire [`MS_TO_FW_BUS_WD -1:0] ms_to_fw_bus;
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wire [`FW_TO_ES_BUS_WD -1:0] fw_to_es_bus;
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wire [`MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
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wire [`WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
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wire es_div_enable;
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wire es_div_sign;
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wire [31:0] es_rf_rdata1;
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wire [31:0] es_rf_rdata2;
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wire div_complete;
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wire [31:0] div_result;
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wire [31:0] mod_result;
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// IF stage
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if_stage if_stage(
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.clk (clk ),
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.reset (reset ),
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//allowin
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.ds_allowin (ds_allowin ),
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//brbus
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.br_bus (br_bus ),
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//outputs
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.fs_to_ds_valid (fs_to_ds_valid ),
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.fs_to_ds_bus (fs_to_ds_bus ),
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// inst sram interface
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.inst_sram_en (inst_sram_en ),
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.inst_sram_wen (inst_sram_we ),
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.inst_sram_addr (inst_sram_addr ),
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.inst_sram_wdata(inst_sram_wdata),
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.inst_sram_rdata(inst_sram_rdata)
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);
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// ID stage
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id_stage id_stage(
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.clk (clk ),
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.reset (reset ),
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//allowin
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.es_allowin (es_allowin ),
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.ds_allowin (ds_allowin ),
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//from fs
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.fs_to_ds_valid (fs_to_ds_valid ),
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.fs_to_ds_bus (fs_to_ds_bus ),
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//to es
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.ds_to_es_valid (ds_to_es_valid ),
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.ds_to_es_bus (ds_to_es_bus ),
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//to rf: for write back
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.ws_to_rf_bus (ws_to_rf_bus ),
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//to fw
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.ds_to_fw_bus (ds_to_fw_bus ),
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//to fs
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.br_bus (br_bus )
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);
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// EXE stage
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exe_stage exe_stage(
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.clk (clk ),
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.reset (reset ),
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//allowin
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.ms_allowin (ms_allowin ),
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.es_allowin (es_allowin ),
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//from ds
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.ds_to_es_valid (ds_to_es_valid ),
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.ds_to_es_bus (ds_to_es_bus ),
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//to ms
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.es_to_ms_valid (es_to_ms_valid ),
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.es_to_ms_bus (es_to_ms_bus ),
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//from fw
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.fw_to_es_bus (fw_to_es_bus ),
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//to fw
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.es_to_fw_bus (es_to_fw_bus ),
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//from ms
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.ms_to_ds_bus (ms_to_es_bus ),
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//from ws
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.ws_to_ds_bus (ws_to_es_bus ),
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// data sram interface
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.data_sram_en (data_sram_en ),
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.data_sram_wen (data_sram_we ),
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.data_sram_addr (data_sram_addr ),
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.data_sram_wdata(data_sram_wdata),
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// div
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.es_div_enable (es_div_enable) ,
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.es_div_sign (es_div_sign) ,
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.es_rf_rdata1 (es_rf_rdata1) ,
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.es_rf_rdata2 (es_rf_rdata2) ,
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.div_complete (div_complete)
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);
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// div
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div u_div(
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.div_clk (clk ),
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.reset (reset ),
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.div (es_div_enable ),
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.div_signed (es_div_sign ),
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.x (es_rf_rdata1 ),
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.y (es_rf_rdata2 ),
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.s (div_result ),
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.r (mod_result ),
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.complete (div_complete )
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);
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// MEM stage
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mem_stage mem_stage(
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.clk (clk ),
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.reset (reset ),
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//allowin
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.ws_allowin (ws_allowin ),
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.ms_allowin (ms_allowin ),
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//from es
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.es_to_ms_valid (es_to_ms_valid ),
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.es_to_ms_bus (es_to_ms_bus ),
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//to ws
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.ms_to_ws_valid (ms_to_ws_valid ),
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.ms_to_ws_bus (ms_to_ws_bus ),
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//from data-sram
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.data_sram_rdata(data_sram_rdata),
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//to fw
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.ms_to_fw_bus (ms_to_fw_bus ),
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//to es
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.ms_to_es_bus (ms_to_es_bus ),
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//div
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.div_result (div_result ),
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.mod_result (mod_result )
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);
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// WB stage
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wb_stage wb_stage(
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.clk (clk ),
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.reset (reset ),
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//allowin
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.ws_allowin (ws_allowin ),
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//from ms
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.ms_to_ws_valid (ms_to_ws_valid ),
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.ms_to_ws_bus (ms_to_ws_bus ),
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//to rf: for write back
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.ws_to_rf_bus (ws_to_rf_bus ),
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//to es
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.ws_to_es_bus (ws_to_es_bus ),
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//trace debug interface
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.debug_wb_pc (debug_wb_pc ),
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.debug_wb_rf_wen (debug_wb_rf_we ),
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.debug_wb_rf_wnum (debug_wb_rf_wnum ),
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.debug_wb_rf_wdata(debug_wb_rf_wdata)
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);
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// Forwarding
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forward forward(
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.clk (clk ),
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.reset (reset ),
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.ds_to_fw_bus (ds_to_fw_bus),
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.es_to_fw_bus (es_to_fw_bus),
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.ms_to_fw_bus (ms_to_fw_bus),
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.fw_to_es_bus (fw_to_es_bus)
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);
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endmodule
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