UnbalancedCat/neulacpu
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[Modified] little bug fix

Browse Source
This commit is contained in:
包焕垲
2023-05-12 21:42:26 +08:00
parent d4366a9c7b
commit 3228082f83
3 changed files with 38 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
lacpu/rtl/cpu/exe_stage.v
View File

@@ -39,19 +39,19 @@ module exe_stage(
wire [31:0] es_imm; wire [31:0] es_imm;
wire [31:0] es_rf_rdata1; wire [31:0] es_rf_rdata1;
wire [31:0] es_rf_rdata2; wire [31:0] es_rf_rdata2;
wire [31:0] es_pc ; wire [31:0] es_pc;
assign {es_alu_op , //158:147 assign {es_alu_op , //166:155
es_src1_is_pc , //146:146 es_src1_is_pc , //154:154
es_src2_is_imm , //145:145 es_src2_is_imm , //153:153
es_src2_is_4 , //144:144 es_src2_is_4 , //152:152
es_mem_to_reg , //143:143 es_mem_to_reg , //151:151
es_reg_we , //142:142 es_reg_we , //150:150
es_mem_we , //141:141 es_mem_we , //149:149
es_load_op , //140:136 es_load_op , //148:142
es_store_op , //135:133 es_store_op , //141:141
es_branch_op , es_branch_op , //141:133
es_dest , //132:128 es_dest , //132:128
es_imm , //127:96 es_imm , //127:96
es_rf_rdata1 , //95 :64 es_rf_rdata1 , //95 :64

20
lacpu/rtl/cpu/id_stage.v
View File

@@ -110,16 +110,16 @@ module id_stage(
wire rj_lt_rd; wire rj_lt_rd;
wire rj_ltu_rd; wire rj_ltu_rd;
assign ds_to_es_bus = {alu_op , //158:147 assign ds_to_es_bus = {alu_op , //166:155
src1_is_pc , //146:146 src1_is_pc , //154:154
src2_is_imm , //145:145 src2_is_imm , //153:153
src2_is_4 , //144:144 src2_is_4 , //152:152
mem_to_reg , //143:143 mem_to_reg , //151:151
reg_we , //142:142 reg_we , //150:150
mem_we , //141:141 mem_we , //149:149
load_op , //140:136 load_op , //148:142
store_op , //135:133 store_op , //141:141
branch_op , branch_op , //141:133
dest , //132:128 dest , //132:128
imm , //127:96 imm , //127:96
rf_rdata1 , //95 :64 rf_rdata1 , //95 :64

2
lacpu/rtl/cpu/mycpu.h
View File

@@ -3,7 +3,7 @@
`define BR_BUS_WD 33 `define BR_BUS_WD 33
`define FS_TO_DS_BUS_WD 64 `define FS_TO_DS_BUS_WD 64
`define DS_TO_ES_BUS_WD 159 `define DS_TO_ES_BUS_WD 167
`define ES_TO_MS_BUS_WD 76 `define ES_TO_MS_BUS_WD 76
`define MS_TO_WS_BUS_WD 70 `define MS_TO_WS_BUS_WD 70
`define WS_TO_RF_BUS_WD 38 `define WS_TO_RF_BUS_WD 38