From 3228082f83c520a3e5e87130e8d6cd785f3b0dee Mon Sep 17 00:00:00 2001 From: UnbalancedCat Date: Fri, 12 May 2023 21:42:26 +0800 Subject: [PATCH] [Modified] little bug fix --- lacpu/rtl/cpu/exe_stage.v | 42 +++++++++++++++++++-------------------- lacpu/rtl/cpu/id_stage.v | 32 ++++++++++++++--------------- lacpu/rtl/cpu/mycpu.h | 2 +- 3 files changed, 38 insertions(+), 38 deletions(-) diff --git a/lacpu/rtl/cpu/exe_stage.v b/lacpu/rtl/cpu/exe_stage.v index 1300a9a..cce01a1 100755 --- a/lacpu/rtl/cpu/exe_stage.v +++ b/lacpu/rtl/cpu/exe_stage.v @@ -39,19 +39,19 @@ module exe_stage( wire [31:0] es_imm; wire [31:0] es_rf_rdata1; wire [31:0] es_rf_rdata2; - wire [31:0] es_pc ; + wire [31:0] es_pc; - assign {es_alu_op , //158:147 - es_src1_is_pc , //146:146 - es_src2_is_imm , //145:145 - es_src2_is_4 , //144:144 - es_mem_to_reg , //143:143 - es_reg_we , //142:142 - es_mem_we , //141:141 - es_load_op , //140:136 - es_store_op , //135:133 - es_branch_op , + assign {es_alu_op , //166:155 + es_src1_is_pc , //154:154 + es_src2_is_imm , //153:153 + es_src2_is_4 , //152:152 + es_mem_to_reg , //151:151 + es_reg_we , //150:150 + es_mem_we , //149:149 + es_load_op , //148:142 + es_store_op , //141:141 + es_branch_op , //141:133 es_dest , //132:128 es_imm , //127:96 es_rf_rdata1 , //95 :64 @@ -97,10 +97,10 @@ module exe_stage( end assign es_alu_src1 = es_src1_is_pc ? es_pc : - es_rf_rdata1; + es_rf_rdata1; assign es_alu_src2 = es_src2_is_imm ? es_imm : - es_src2_is_4 ? 32'd4 : - es_rf_rdata2; + es_src2_is_4 ? 32'd4 : + es_rf_rdata2; alu u_alu( .alu_op (es_alu_op ), @@ -116,13 +116,13 @@ module exe_stage( assign data_sram_en = 1'b1; assign data_sram_wen = (es_mem_we && es_valid) ? (({4{es_store_op[0]}} & ({4{es_alu_result[1:0] == 2'b00}} & 4'b0001) - | ({4{es_alu_result[1:0] == 2'b01}} & 4'b0010) - | ({4{es_alu_result[1:0] == 2'b10}} & 4'b0100) - | ({4{es_alu_result[1:0] == 2'b11}} & 4'b1000)) - | ({4{es_store_op[1]}} & ({4{es_alu_result[1:0] == 2'b01}} & 4'b0011) - | ({4{es_alu_result[1:0] == 2'b10}} & 4'b1100)) - | ({4{es_store_op[2]}} & 4'b1111 )) - : 4'b0000; + | ({4{es_alu_result[1:0] == 2'b01}} & 4'b0010) + | ({4{es_alu_result[1:0] == 2'b10}} & 4'b0100) + | ({4{es_alu_result[1:0] == 2'b11}} & 4'b1000)) + | ({4{es_store_op[1]}} & ({4{es_alu_result[1:0] == 2'b01}} & 4'b0011) + | ({4{es_alu_result[1:0] == 2'b10}} & 4'b1100)) + | ({4{es_store_op[2]}} & 4'b1111 )) + : 4'b0000; assign data_sram_addr = es_alu_result; assign data_sram_wdata = es_store_op[0] ? {4{es_rf_rdata2[ 7:0]}} : diff --git a/lacpu/rtl/cpu/id_stage.v b/lacpu/rtl/cpu/id_stage.v index 155c922..a11cc2a 100755 --- a/lacpu/rtl/cpu/id_stage.v +++ b/lacpu/rtl/cpu/id_stage.v @@ -110,22 +110,22 @@ module id_stage( wire rj_lt_rd; wire rj_ltu_rd; - assign ds_to_es_bus = {alu_op , //158:147 - src1_is_pc , //146:146 - src2_is_imm , //145:145 - src2_is_4 , //144:144 - mem_to_reg , //143:143 - reg_we , //142:142 - mem_we , //141:141 - load_op , //140:136 - store_op , //135:133 - branch_op , - dest , //132:128 - imm , //127:96 - rf_rdata1 , //95 :64 - rf_rdata2 , //63 :32 - ds_pc //31 :0 - }; + assign ds_to_es_bus = {alu_op , //166:155 + src1_is_pc , //154:154 + src2_is_imm , //153:153 + src2_is_4 , //152:152 + mem_to_reg , //151:151 + reg_we , //150:150 + mem_we , //149:149 + load_op , //148:142 + store_op , //141:141 + branch_op , //141:133 + dest , //132:128 + imm , //127:96 + rf_rdata1 , //95 :64 + rf_rdata2 , //63 :32 + ds_pc //31 :0 + }; assign ds_ready_go = 1'b1; diff --git a/lacpu/rtl/cpu/mycpu.h b/lacpu/rtl/cpu/mycpu.h index 86be33e..f0cde5a 100755 --- a/lacpu/rtl/cpu/mycpu.h +++ b/lacpu/rtl/cpu/mycpu.h @@ -3,7 +3,7 @@ `define BR_BUS_WD 33 `define FS_TO_DS_BUS_WD 64 - `define DS_TO_ES_BUS_WD 159 + `define DS_TO_ES_BUS_WD 167 `define ES_TO_MS_BUS_WD 76 `define MS_TO_WS_BUS_WD 70 `define WS_TO_RF_BUS_WD 38