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[Add] add loaduse.v & fix little bug

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包焕垲
2023-05-28 16:53:31 +08:00
parent 3b43e06054
commit 144623175a
4 changed files with 70 additions and 20 deletions
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40
lacpu/rtl/cpu/exe_stage.v
View File

@@ -190,15 +190,15 @@ module exe_stage(
always @(posedge clk) begin
if(reset) begin
div_divisor_valid_reg <= 0'b0;
div_divisor_ready_flag <= 0'b0;
div_divisor_valid_reg <= 1'b0;
div_divisor_ready_flag <= 1'b0;
end
else if(div_divisor_valid_reg && div_divisor_ready) begin
div_divisor_valid_reg <= 0'b0;
div_divisor_ready_flag <= 0'b1;
div_divisor_valid_reg <= 1'b0;
div_divisor_ready_flag <= 1'b1;
end
else if((es_inst_divw || es_inst_modw) && !div_divisor_ready_flag) begin
div_divisor_valid_reg <= 0'b1;
div_divisor_valid_reg <= 1'b1;
end
else if(es_ready_go) begin
div_divisor_ready_flag <= 1'b0;
@@ -206,15 +206,15 @@ module exe_stage(
end
always @(posedge clk) begin
if(reset) begin
div_dividend_valid_reg <= 0'b0;
div_dividend_ready_flag <= 0'b0;
div_dividend_valid_reg <= 1'b0;
div_dividend_ready_flag <= 1'b0;
end
else if(div_dividend_valid_reg && div_dividend_ready) begin
div_dividend_valid_reg <= 0'b0;
div_dividend_ready_flag <= 0'b1;
div_dividend_valid_reg <= 1'b0;
div_dividend_ready_flag <= 1'b1;
end
else if((es_inst_divw || es_inst_modw) && !div_dividend_ready_flag) begin
div_dividend_valid_reg <= 0'b1;
div_dividend_valid_reg <= 1'b1;
end
else if(es_ready_go) begin
div_dividend_ready_flag <= 1'b0;
@@ -222,15 +222,15 @@ module exe_stage(
end
always @(posedge clk) begin
if(reset) begin
divu_divisor_valid_reg <= 0'b0;
divu_divisor_ready_flag <= 0'b0;
divu_divisor_valid_reg <= 1'b0;
divu_divisor_ready_flag <= 1'b0;
end
else if(divu_divisor_valid_reg && divu_divisor_ready) begin
divu_divisor_valid_reg <= 0'b0;
divu_divisor_ready_flag <= 0'b1;
divu_divisor_valid_reg <= 1'b0;
divu_divisor_ready_flag <= 1'b1;
end
else if((es_inst_divw || es_inst_modw) && !divu_divisor_ready_flag) begin
divu_divisor_valid_reg <= 0'b1;
divu_divisor_valid_reg <= 1'b1;
end
else if(es_ready_go) begin
divu_divisor_ready_flag <= 1'b0;
@@ -238,15 +238,15 @@ module exe_stage(
end
always @(posedge clk) begin
if(reset) begin
divu_dividend_valid_reg <= 0'b0;
divu_dividend_ready_flag <= 0'b0;
divu_dividend_valid_reg <= 1'b0;
divu_dividend_ready_flag <= 1'b0;
end
else if(divu_dividend_valid_reg && divu_dividend_ready) begin
divu_dividend_valid_reg <= 0'b0;
divu_dividend_ready_flag <= 0'b1;
divu_dividend_valid_reg <= 1'b0;
divu_dividend_ready_flag <= 1'b1;
end
else if((es_inst_divw || es_inst_modw) && !divu_dividend_ready_flag) begin
divu_dividend_valid_reg <= 0'b1;
divu_dividend_valid_reg <= 1'b1;
end
else if(es_ready_go) begin
divu_dividend_ready_flag <= 1'b0;

39
lacpu/rtl/cpu/loaduse.v Normal file
View File

@@ -0,0 +1,39 @@
`include "mycpu.v"
module loaduse(
input clk,
input reset,
input [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus,
input [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus,
output loaduse
);
wire [4:0] ds_rf_raddr1;
wire [4:0] ds_rf_raddr2;
wire [4:0] es_load_op;
wire [4:0] es_dest;
reg [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus_reg;
reg [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus_reg;
wire loaduse;
always @(posedge clk) begin
if(reset) begin
ds_to_lu_bus_reg <= 0;
es_to_lu_bus_reg <= 0;
end
else begin
ds_to_lu_bus_reg <= ds_to_lu_bus;
es_to_lu_bus_reg <= es_to_lu_bus;
end
end
assign {ds_rf_rdata1, ds_rf_rdata2} = ds_to_lu_bus_reg;
assign {es_dest , es_load_op } = es_to_lu_bus_reg;
assign loaduse = ^es_load_op &&
(((ds_rf_rdata1 == es_dest) && (ds_rf_rdata1 != 5'b0)) || ((ds_rf_rdata2 == es_dest) && (ds_rf_rdata2 != 5'b0)));
endmodule

3
lacpu/rtl/cpu/mycpu.v
View File

@@ -15,4 +15,7 @@
`define MS_TO_ES_BUS_WD 32
`define WS_TO_ES_BUS_WD 32
`define DS_TO_LU_BUS_WD 10
`define ES_TO_LU_BUS_WD 10
`endif