From 144623175ac7fd92503fea1cef197e507693671e Mon Sep 17 00:00:00 2001 From: UnbalancedCat Date: Sun, 28 May 2023 16:53:31 +0800 Subject: [PATCH] [Add] add loaduse.v & fix little bug --- lacpu/rtl/cpu/exe_stage.v | 40 ++++++++++++++++---------------- lacpu/rtl/cpu/loaduse.v | 39 +++++++++++++++++++++++++++++++ lacpu/rtl/cpu/mycpu.v | 3 +++ lacpu/run_vivado/la32r/la32r.xpr | 8 +++++++ 4 files changed, 70 insertions(+), 20 deletions(-) create mode 100644 lacpu/rtl/cpu/loaduse.v diff --git a/lacpu/rtl/cpu/exe_stage.v b/lacpu/rtl/cpu/exe_stage.v index 8fe8d8f..2669e7f 100755 --- a/lacpu/rtl/cpu/exe_stage.v +++ b/lacpu/rtl/cpu/exe_stage.v @@ -190,15 +190,15 @@ module exe_stage( always @(posedge clk) begin if(reset) begin - div_divisor_valid_reg <= 0'b0; - div_divisor_ready_flag <= 0'b0; + div_divisor_valid_reg <= 1'b0; + div_divisor_ready_flag <= 1'b0; end else if(div_divisor_valid_reg && div_divisor_ready) begin - div_divisor_valid_reg <= 0'b0; - div_divisor_ready_flag <= 0'b1; + div_divisor_valid_reg <= 1'b0; + div_divisor_ready_flag <= 1'b1; end else if((es_inst_divw || es_inst_modw) && !div_divisor_ready_flag) begin - div_divisor_valid_reg <= 0'b1; + div_divisor_valid_reg <= 1'b1; end else if(es_ready_go) begin div_divisor_ready_flag <= 1'b0; @@ -206,15 +206,15 @@ module exe_stage( end always @(posedge clk) begin if(reset) begin - div_dividend_valid_reg <= 0'b0; - div_dividend_ready_flag <= 0'b0; + div_dividend_valid_reg <= 1'b0; + div_dividend_ready_flag <= 1'b0; end else if(div_dividend_valid_reg && div_dividend_ready) begin - div_dividend_valid_reg <= 0'b0; - div_dividend_ready_flag <= 0'b1; + div_dividend_valid_reg <= 1'b0; + div_dividend_ready_flag <= 1'b1; end else if((es_inst_divw || es_inst_modw) && !div_dividend_ready_flag) begin - div_dividend_valid_reg <= 0'b1; + div_dividend_valid_reg <= 1'b1; end else if(es_ready_go) begin div_dividend_ready_flag <= 1'b0; @@ -222,15 +222,15 @@ module exe_stage( end always @(posedge clk) begin if(reset) begin - divu_divisor_valid_reg <= 0'b0; - divu_divisor_ready_flag <= 0'b0; + divu_divisor_valid_reg <= 1'b0; + divu_divisor_ready_flag <= 1'b0; end else if(divu_divisor_valid_reg && divu_divisor_ready) begin - divu_divisor_valid_reg <= 0'b0; - divu_divisor_ready_flag <= 0'b1; + divu_divisor_valid_reg <= 1'b0; + divu_divisor_ready_flag <= 1'b1; end else if((es_inst_divw || es_inst_modw) && !divu_divisor_ready_flag) begin - divu_divisor_valid_reg <= 0'b1; + divu_divisor_valid_reg <= 1'b1; end else if(es_ready_go) begin divu_divisor_ready_flag <= 1'b0; @@ -238,15 +238,15 @@ module exe_stage( end always @(posedge clk) begin if(reset) begin - divu_dividend_valid_reg <= 0'b0; - divu_dividend_ready_flag <= 0'b0; + divu_dividend_valid_reg <= 1'b0; + divu_dividend_ready_flag <= 1'b0; end else if(divu_dividend_valid_reg && divu_dividend_ready) begin - divu_dividend_valid_reg <= 0'b0; - divu_dividend_ready_flag <= 0'b1; + divu_dividend_valid_reg <= 1'b0; + divu_dividend_ready_flag <= 1'b1; end else if((es_inst_divw || es_inst_modw) && !divu_dividend_ready_flag) begin - divu_dividend_valid_reg <= 0'b1; + divu_dividend_valid_reg <= 1'b1; end else if(es_ready_go) begin divu_dividend_ready_flag <= 1'b0; diff --git a/lacpu/rtl/cpu/loaduse.v b/lacpu/rtl/cpu/loaduse.v new file mode 100644 index 0000000..9218223 --- /dev/null +++ b/lacpu/rtl/cpu/loaduse.v @@ -0,0 +1,39 @@ +`include "mycpu.v" + +module loaduse( + input clk, + input reset, + + input [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus, + input [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus, + + output loaduse +); + wire [4:0] ds_rf_raddr1; + wire [4:0] ds_rf_raddr2; + wire [4:0] es_load_op; + wire [4:0] es_dest; + + reg [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus_reg; + reg [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus_reg; + + wire loaduse; + + always @(posedge clk) begin + if(reset) begin + ds_to_lu_bus_reg <= 0; + es_to_lu_bus_reg <= 0; + end + else begin + ds_to_lu_bus_reg <= ds_to_lu_bus; + es_to_lu_bus_reg <= es_to_lu_bus; + end + end + + + assign {ds_rf_rdata1, ds_rf_rdata2} = ds_to_lu_bus_reg; + assign {es_dest , es_load_op } = es_to_lu_bus_reg; + + assign loaduse = ^es_load_op && + (((ds_rf_rdata1 == es_dest) && (ds_rf_rdata1 != 5'b0)) || ((ds_rf_rdata2 == es_dest) && (ds_rf_rdata2 != 5'b0))); +endmodule \ No newline at end of file diff --git a/lacpu/rtl/cpu/mycpu.v b/lacpu/rtl/cpu/mycpu.v index 7d36e7f..52703ea 100644 --- a/lacpu/rtl/cpu/mycpu.v +++ b/lacpu/rtl/cpu/mycpu.v @@ -15,4 +15,7 @@ `define MS_TO_ES_BUS_WD 32 `define WS_TO_ES_BUS_WD 32 + + `define DS_TO_LU_BUS_WD 10 + `define ES_TO_LU_BUS_WD 10 `endif diff --git a/lacpu/run_vivado/la32r/la32r.xpr b/lacpu/run_vivado/la32r/la32r.xpr index 35869af..bb50bde 100644 --- a/lacpu/run_vivado/la32r/la32r.xpr +++ b/lacpu/run_vivado/la32r/la32r.xpr @@ -152,6 +152,14 @@ + + + + + + + +