final submit
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@@ -49,7 +49,8 @@ module mycpu_core
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always @(posedge clk) reset <= ~resetn;
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wire [FS_TO_DS_BUS_WD -1:0] fs1_to_fs2_bus;
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wire [FS_TO_DS_BUS_WD -1:0] fs2_to_ds_bus;
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wire [FS_TO_DS_BUS_WD -1:0] fs2_to_fs3_bus;
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wire [FS_TO_DS_BUS_WD -1:0] fs3_to_ds_bus;
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wire [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
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wire [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus;
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wire [DT_TO_MS_BUS_WD -1:0] dts_to_ms1_bus;
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@@ -116,11 +117,7 @@ module mycpu_core
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.stall (stall ),
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.new_pc (new_pc ),
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.fs1_to_fs2_bus (fs1_to_fs2_bus ),
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.br_bus (br_bus_real ),
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.inst_sram_en (inst_sram_en ),
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.inst_sram_we (inst_sram_we ),
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.inst_sram_addr (inst_sram_addr ),
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.inst_sram_wdata (inst_sram_wdata )
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.br_bus (br_bus_real )
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);
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if2_stage if2_stage(
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@@ -131,7 +128,23 @@ module mycpu_core
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.br_taken (br_taken ),
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.fs1_to_fs2_bus (fs1_to_fs2_bus ),
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.fs2_to_ds_bus (fs2_to_ds_bus )
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.fs2_to_fs3_bus (fs2_to_fs3_bus ),
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.inst_sram_en (inst_sram_en ),
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.inst_sram_we (inst_sram_we ),
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.inst_sram_addr (inst_sram_addr ),
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.inst_sram_wdata (inst_sram_wdata )
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);
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if3_stage if3_stage(
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.clk (clk ),
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.reset (reset ),
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.flush (flush ),
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.stall (stall ),
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.br_taken (br_taken ),
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.fs2_to_fs3_bus (fs2_to_fs3_bus ),
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.fs3_to_ds_bus (fs3_to_ds_bus )
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);
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id_stage id_stage(
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@@ -141,7 +154,7 @@ module mycpu_core
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.stall (stall ),
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.br_taken (br_taken ),
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.stallreq_ds (stallreq_ds ),
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.fs2_to_ds_bus (fs2_to_ds_bus ),
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.fs3_to_ds_bus (fs3_to_ds_bus ),
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.inst_sram_rdata (inst_sram_rdata ),
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.csr_plv (csr_plv ),
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.csr_has_int (csr_has_int ),
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