diff --git a/lacpu/doc/design-初赛.docx b/lacpu/doc/design-初赛.docx deleted file mode 100644 index 1bcc33a..0000000 Binary files a/lacpu/doc/design-初赛.docx and /dev/null differ diff --git a/lacpu/doc/design.docx b/lacpu/doc/design.docx new file mode 100644 index 0000000..303fa92 Binary files /dev/null and b/lacpu/doc/design.docx differ diff --git a/lacpu/doc/mycpu性能计算.xlsx b/lacpu/doc/mycpu性能计算.xlsx index 826cdce..f734020 100644 Binary files a/lacpu/doc/mycpu性能计算.xlsx and b/lacpu/doc/mycpu性能计算.xlsx differ diff --git a/lacpu/doc/流水线设计.vsdx b/lacpu/doc/流水线设计.vsdx index 0f93f9c..a89ca35 100644 Binary files a/lacpu/doc/流水线设计.vsdx and b/lacpu/doc/流水线设计.vsdx differ diff --git a/lacpu/rtl/mycpu/csr.v b/lacpu/rtl/mycpu/csr.v index 158e819..66d79ad 100644 --- a/lacpu/rtl/mycpu/csr.v +++ b/lacpu/rtl/mycpu/csr.v @@ -1,4 +1,4 @@ -`include "csr.hv" +`include "csr.vh" module csr( input clk, input reset, @@ -249,8 +249,8 @@ module csr( end `EUEN_ADDR : euen <= csr_wdata_temp; `ECFG_ADDR : begin - ecfg <= csr_wdata_temp; // ???????????????? - + ecfg[ `LIE_1] <= csr_wdata_temp[ `LIE_1]; + ecfg[ `LIE_2] <= csr_wdata_temp[ `LIE_2]; end `ESTAT_ADDR : estat[1:0] <= csr_wdata_temp[1:0]; `ERA_ADDR : era <= csr_wdata_temp; diff --git a/lacpu/rtl/mycpu/csr.hv b/lacpu/rtl/mycpu/csr.vh similarity index 100% rename from lacpu/rtl/mycpu/csr.hv rename to lacpu/rtl/mycpu/csr.vh diff --git a/lacpu/rtl/mycpu/id_stage.v b/lacpu/rtl/mycpu/id_stage.v index 96b59b6..704b8f9 100644 --- a/lacpu/rtl/mycpu/id_stage.v +++ b/lacpu/rtl/mycpu/id_stage.v @@ -19,7 +19,7 @@ module id_stage input [ 1:0] csr_plv, input csr_has_int, - input [FS_TO_DS_BUS_WD -1:0] fs2_to_ds_bus, + input [FS_TO_DS_BUS_WD -1:0] fs3_to_ds_bus, input [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus, output [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus ); @@ -140,12 +140,12 @@ module id_stage stall_flag <= 0; end else if ((!stall[1]) & stall_flag) begin - fs2_to_ds_bus_r <= fs2_to_ds_bus; + fs2_to_ds_bus_r <= fs3_to_ds_bus; inst_sram_rdata_r <= inst_sram_rdata_buffer; stall_flag <= 0; end else if ((!stall[1]) & (!stall_flag)) begin - fs2_to_ds_bus_r <= fs2_to_ds_bus; + fs2_to_ds_bus_r <= fs3_to_ds_bus; inst_sram_rdata_r <= inst_sram_rdata; stall_flag <= 0; end diff --git a/lacpu/rtl/mycpu/if_stage.v b/lacpu/rtl/mycpu/if_stage.v index 39c604b..ea6ee67 100644 --- a/lacpu/rtl/mycpu/if_stage.v +++ b/lacpu/rtl/mycpu/if_stage.v @@ -12,10 +12,10 @@ module if1_stage input [31:0] new_pc, - output inst_sram_en , - output [ 3:0] inst_sram_we , - output [31:0] inst_sram_addr , - output [31:0] inst_sram_wdata, + // output inst_sram_en , + // output [ 3:0] inst_sram_we , + // output [31:0] inst_sram_addr , + // output [31:0] inst_sram_wdata, input [BR_BUS_WD -1:0] br_bus, output [FS_TO_DS_BUS_WD -1:0] fs1_to_fs2_bus @@ -32,9 +32,9 @@ module if1_stage wire [31:0] br_target; - assign fs1_to_fs2_bus = {inst_sram_en, //33:33 - excp_adef, //32:32 - fs_pc //31:0 + assign fs1_to_fs2_bus = {(br_taken ? 1'b0 : pc_valid), //33:33 + excp_adef, //32:32 + fs_pc //31:0 }; assign {br_taken, @@ -62,10 +62,10 @@ module if1_stage assign seq_pc = fs_pc + 3'h4; assign next_pc = br_taken ? br_target : seq_pc; - assign inst_sram_en = br_taken ? 1'b0 : pc_valid; - assign inst_sram_we = 4'h0; - assign inst_sram_addr = fs_pc; - assign inst_sram_wdata = 32'b0; + // assign inst_sram_en = br_taken ? 1'b0 : pc_valid; + // assign inst_sram_we = 4'h0; + // assign inst_sram_addr = fs_pc; + // assign inst_sram_wdata = 32'b0; endmodule module if2_stage @@ -82,15 +82,24 @@ module if2_stage input br_taken, input [FS_TO_DS_BUS_WD -1:0] fs1_to_fs2_bus, - output [FS_TO_DS_BUS_WD -1:0] fs2_to_ds_bus + output [FS_TO_DS_BUS_WD -1:0] fs2_to_fs3_bus, + + output inst_sram_en , + output [ 3:0] inst_sram_we , + output [31:0] inst_sram_addr , + output [31:0] inst_sram_wdata ); reg [FS_TO_DS_BUS_WD -1:0] fs1_to_fs2_bus_r; - wire br_flush; + wire br_flush; + wire [31:0] fs_pc; + wire pc_valid; assign br_flush = br_taken; + assign fs_pc = fs1_to_fs2_bus_r[31:0]; + assign pc_valid = fs1_to_fs2_bus_r[33]; - assign fs2_to_ds_bus = fs1_to_fs2_bus_r; + assign fs2_to_fs3_bus = fs1_to_fs2_bus_r; always @ (posedge clk) begin if (reset) begin @@ -107,4 +116,49 @@ module if2_stage end end + assign inst_sram_en = br_taken ? 1'b0 : pc_valid; + assign inst_sram_we = 4'h0; + assign inst_sram_addr = fs_pc; + assign inst_sram_wdata = 32'b0; + +endmodule + +module if3_stage +#( + parameter FS_TO_DS_BUS_WD = 34 +) +( + input clk , + input reset, + + input flush, + input [ 5:0] stall, + + input br_taken, + input [FS_TO_DS_BUS_WD -1:0] fs2_to_fs3_bus, + + output [FS_TO_DS_BUS_WD -1:0] fs3_to_ds_bus +); + reg [FS_TO_DS_BUS_WD -1:0] fs2_to_fs3_bus_r; + + wire br_flush; + + assign br_flush = br_taken; + + assign fs3_to_ds_bus = fs2_to_fs3_bus_r; + + always @ (posedge clk) begin + if (reset) begin + fs2_to_fs3_bus_r <= 0; + end + else if (flush | br_flush) begin + fs2_to_fs3_bus_r <= 0; + end + else if (stall[0] & !stall[1]) begin + fs2_to_fs3_bus_r <= 0; + end + else if (!stall[0]) begin + fs2_to_fs3_bus_r <= fs2_to_fs3_bus; + end + end endmodule \ No newline at end of file diff --git a/lacpu/rtl/mycpu/mycpu_core.v b/lacpu/rtl/mycpu/mycpu_core.v index 8983046..2ece76b 100644 --- a/lacpu/rtl/mycpu/mycpu_core.v +++ b/lacpu/rtl/mycpu/mycpu_core.v @@ -49,7 +49,8 @@ module mycpu_core always @(posedge clk) reset <= ~resetn; wire [FS_TO_DS_BUS_WD -1:0] fs1_to_fs2_bus; - wire [FS_TO_DS_BUS_WD -1:0] fs2_to_ds_bus; + wire [FS_TO_DS_BUS_WD -1:0] fs2_to_fs3_bus; + wire [FS_TO_DS_BUS_WD -1:0] fs3_to_ds_bus; wire [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus; wire [ES_TO_DT_BUS_WD -1:0] es_to_dts_bus; wire [DT_TO_MS_BUS_WD -1:0] dts_to_ms1_bus; @@ -116,11 +117,7 @@ module mycpu_core .stall (stall ), .new_pc (new_pc ), .fs1_to_fs2_bus (fs1_to_fs2_bus ), - .br_bus (br_bus_real ), - .inst_sram_en (inst_sram_en ), - .inst_sram_we (inst_sram_we ), - .inst_sram_addr (inst_sram_addr ), - .inst_sram_wdata (inst_sram_wdata ) + .br_bus (br_bus_real ) ); if2_stage if2_stage( @@ -131,7 +128,23 @@ module mycpu_core .br_taken (br_taken ), .fs1_to_fs2_bus (fs1_to_fs2_bus ), - .fs2_to_ds_bus (fs2_to_ds_bus ) + .fs2_to_fs3_bus (fs2_to_fs3_bus ), + + .inst_sram_en (inst_sram_en ), + .inst_sram_we (inst_sram_we ), + .inst_sram_addr (inst_sram_addr ), + .inst_sram_wdata (inst_sram_wdata ) + ); + + if3_stage if3_stage( + .clk (clk ), + .reset (reset ), + .flush (flush ), + .stall (stall ), + + .br_taken (br_taken ), + .fs2_to_fs3_bus (fs2_to_fs3_bus ), + .fs3_to_ds_bus (fs3_to_ds_bus ) ); id_stage id_stage( @@ -141,7 +154,7 @@ module mycpu_core .stall (stall ), .br_taken (br_taken ), .stallreq_ds (stallreq_ds ), - .fs2_to_ds_bus (fs2_to_ds_bus ), + .fs3_to_ds_bus (fs3_to_ds_bus ), .inst_sram_rdata (inst_sram_rdata ), .csr_plv (csr_plv ), .csr_has_int (csr_has_int ), diff --git a/lacpu/rtl/mycpu/tlb.v b/lacpu/rtl/mycpu/tlb.v deleted file mode 100644 index eae81bd..0000000 --- a/lacpu/rtl/mycpu/tlb.v +++ /dev/null @@ -1,182 +0,0 @@ -module tlb -( - input clk, - - //search port 1 - input [12:0] s0_vppn, - input [9:0] s0_asid, - input s0_odd, - output reg [11:0] s0_ppn, - output reg [3:0] s0_index, - output reg s0_found, - //search port 2 - input [12:0] s1_vppn, - input [9:0] s1_asid, - input s1_odd, - output reg [11:0] s1_ppn, - output reg [3:0] s1_index, - output reg s1_found, - - //read port - input [3:0] r_index, - output [12:0] r_vppn, - output [5:0] r_ps, - output r_g, - output [9:0] r_asid, - output r_e, - output [11:0] r_ppn0, - output [1:0] r_plv0, - output [1:0] r_mat0, - output r_d0, - output r_v0, - output [11:0] r_ppn1, - output [1:0] r_plv1, - output [1:0] r_mat1, - output r_d1, - output r_v1, - - - //write port - input we, - input [3:0] w_index, - input [12:0] w_vppn, - input [5:0] w_ps, - input w_g, - input [9:0] w_asid, - input w_e, - input [11:0] w_ppn0, - input [1:0] w_plv0, - input [1:0] w_mat0, - input w_d0, - input w_v0, - input [11:0] w_ppn1, - input [1:0] w_plv1, - input [1:0] w_mat1, - input w_d1, - input w_v1 - -); - -reg [12:0] tlb_vppn [0:15]; -reg [5:0] tlb_ps [0:15]; -reg tlb_g [0:15]; -reg [9:0] tlb_asid [0:15]; -reg tlb_e [0:15]; -reg [11:0] tlb_ppn0 [0:15]; -reg [1:0] tlb_plv0 [0:15]; -reg [1:0] tlb_mat0 [0:15]; -reg tlb_d0 [0:15]; -reg tlb_v0 [0:15]; -reg [11:0] tlb_ppn1 [0:15]; -reg [1:0] tlb_plv1 [0:15]; -reg [1:0] tlb_mat1 [0:15]; -reg tlb_d1 [0:15]; -reg tlb_v1 [0:15]; - - -//search -integer i; -reg match0 [0:15]; -reg match1 [0:15]; -always @(*) begin - for(i = 0; i < 16; i++) begin - match0[i] = (s0_vppn == tlb_vppn[i]) && ((s0_asid == tlb_asid[i]) || tlb_g[i]); - match1[i] = (s1_vppn == tlb_vppn[i]) && ((s1_asid == tlb_asid[i]) || tlb_g[i]); - end -end - -always @(*) begin - s0_found = match0[0]; - s1_found = match1[0]; - for(i = 1; i < 16; i++) begin - s0_found = match0[i] || s0_found; - s1_found = match1[i] || s1_found; - end -end - -always @(*) begin - case (1'b1) - match0[0]: begin s0_ppn = s0_odd ? tlb_ppn0[0] : tlb_ppn1[0]; s0_index = 4'd0; end - match0[1]: begin s0_ppn = s0_odd ? tlb_ppn0[1] : tlb_ppn1[1]; s0_index = 4'd1; end - match0[2]: begin s0_ppn = s0_odd ? tlb_ppn0[2] : tlb_ppn1[2]; s0_index = 4'd2; end - match0[3]: begin s0_ppn = s0_odd ? tlb_ppn0[3] : tlb_ppn1[3]; s0_index = 4'd3; end - match0[4]: begin s0_ppn = s0_odd ? tlb_ppn0[4] : tlb_ppn1[4]; s0_index = 4'd4; end - match0[5]: begin s0_ppn = s0_odd ? tlb_ppn0[5] : tlb_ppn1[5]; s0_index = 4'd5; end - match0[6]: begin s0_ppn = s0_odd ? tlb_ppn0[6] : tlb_ppn1[6]; s0_index = 4'd6; end - match0[7]: begin s0_ppn = s0_odd ? tlb_ppn0[7] : tlb_ppn1[7]; s0_index = 4'd7; end - match0[8]: begin s0_ppn = s0_odd ? tlb_ppn0[8] : tlb_ppn1[8]; s0_index = 4'd8; end - match0[9]: begin s0_ppn = s0_odd ? tlb_ppn0[9] : tlb_ppn1[9]; s0_index = 4'd9; end - match0[10]: begin s0_ppn = s0_odd ? tlb_ppn0[10] : tlb_ppn1[10]; s0_index = 4'd10; end - match0[11]: begin s0_ppn = s0_odd ? tlb_ppn0[11] : tlb_ppn1[11]; s0_index = 4'd11; end - match0[12]: begin s0_ppn = s0_odd ? tlb_ppn0[12] : tlb_ppn1[12]; s0_index = 4'd12; end - match0[13]: begin s0_ppn = s0_odd ? tlb_ppn0[13] : tlb_ppn1[13]; s0_index = 4'd13; end - match0[14]: begin s0_ppn = s0_odd ? tlb_ppn0[14] : tlb_ppn1[14]; s0_index = 4'd14; end - match0[15]: begin s0_ppn = s0_odd ? tlb_ppn0[15] : tlb_ppn1[15]; s0_index = 4'd15; end - default: begin - s0_ppn = 12'b0; - s0_index = 4'd0; - end - endcase - - case (1'b1) - match1[0]: begin s1_ppn = s1_odd ? tlb_ppn0[0] : tlb_ppn1[0]; s1_index = 4'd0; end - match1[1]: begin s1_ppn = s1_odd ? tlb_ppn0[1] : tlb_ppn1[1]; s1_index = 4'd1; end - match1[2]: begin s1_ppn = s1_odd ? tlb_ppn0[2] : tlb_ppn1[2]; s1_index = 4'd2; end - match1[3]: begin s1_ppn = s1_odd ? tlb_ppn0[3] : tlb_ppn1[3]; s1_index = 4'd3; end - match1[4]: begin s1_ppn = s1_odd ? tlb_ppn0[4] : tlb_ppn1[4]; s1_index = 4'd4; end - match1[5]: begin s1_ppn = s1_odd ? tlb_ppn0[5] : tlb_ppn1[5]; s1_index = 4'd5; end - match1[6]: begin s1_ppn = s1_odd ? tlb_ppn0[6] : tlb_ppn1[6]; s1_index = 4'd6; end - match1[7]: begin s1_ppn = s1_odd ? tlb_ppn0[7] : tlb_ppn1[7]; s1_index = 4'd7; end - match1[8]: begin s1_ppn = s1_odd ? tlb_ppn0[8] : tlb_ppn1[8]; s1_index = 4'd8; end - match1[9]: begin s1_ppn = s1_odd ? tlb_ppn0[9] : tlb_ppn1[9]; s1_index = 4'd9; end - match1[10]: begin s1_ppn = s1_odd ? tlb_ppn0[10] : tlb_ppn1[10]; s1_index = 4'd10; end - match1[11]: begin s1_ppn = s1_odd ? tlb_ppn0[11] : tlb_ppn1[11]; s1_index = 4'd11; end - match1[12]: begin s1_ppn = s1_odd ? tlb_ppn0[12] : tlb_ppn1[12]; s1_index = 4'd12; end - match1[13]: begin s1_ppn = s1_odd ? tlb_ppn0[13] : tlb_ppn1[13]; s1_index = 4'd13; end - match1[14]: begin s1_ppn = s1_odd ? tlb_ppn0[14] : tlb_ppn1[14]; s1_index = 4'd14; end - match1[15]: begin s1_ppn = s1_odd ? tlb_ppn0[15] : tlb_ppn1[15]; s1_index = 4'd15; end - default: begin - s1_ppn = 12'b0; - end - endcase -end - -//read -assign r_vppn = (we && w_index == r_index) ? w_vppn : tlb_vppn[r_index]; -assign r_ps = (we && w_index == r_index) ? w_ps : tlb_ps[r_index]; -assign r_g = (we && w_index == r_index) ? w_g : tlb_g[r_index]; -assign r_asid = (we && w_index == r_index) ? w_asid : tlb_asid[r_index]; -assign r_e = (we && w_index == r_index) ? w_e : tlb_e[r_index]; -assign r_ppn0 = (we && w_index == r_index) ? w_ppn0 : tlb_ppn0[r_index]; -assign r_plv0 = (we && w_index == r_index) ? w_plv0 : tlb_plv0[r_index]; -assign r_mat0 = (we && w_index == r_index) ? w_mat0 : tlb_mat0[r_index]; -assign r_d0 = (we && w_index == r_index) ? w_d0 : tlb_d0[r_index]; -assign r_v0 = (we && w_index == r_index) ? w_v0 : tlb_v0[r_index]; -assign r_ppn1 = (we && w_index == r_index) ? w_ppn1 : tlb_ppn1[r_index]; -assign r_plv1 = (we && w_index == r_index) ? w_plv1 : tlb_plv1[r_index]; -assign r_mat1 = (we && w_index == r_index) ? w_mat1 : tlb_mat1[r_index]; -assign r_d1 = (we && w_index == r_index) ? w_d1 : tlb_d1[r_index]; -assign r_v1 = (we && w_index == r_index) ? w_v1 : tlb_v1[r_index]; - -//write -always @(posedge clk) begin - if(we) begin - tlb_vppn[w_index] <= w_vppn; - tlb_ps[w_index] <= w_ps; - tlb_g[w_index] <= w_g; - tlb_asid[w_index] <= w_asid; - tlb_e[w_index] <= w_e; - tlb_ppn0[w_index] <= w_ppn0; - tlb_plv0[w_index] <= w_plv0; - tlb_mat0[w_index] <= w_mat0; - tlb_d0[w_index] <= w_d0; - tlb_v0[w_index] <= w_v0; - tlb_ppn1[w_index] <= w_ppn1; - tlb_plv1[w_index] <= w_plv1; - tlb_mat1[w_index] <= w_mat1; - tlb_d1[w_index] <= w_d1; - tlb_v1[w_index] <= w_v1; - end -end - -endmodule