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包焕垲
2023-08-17 11:31:28 +08:00
parent f17a44883f
commit 0f65e8f6cc
10 changed files with 95 additions and 210 deletions
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6
lacpu/rtl/mycpu/csr.v
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@@ -1,4 +1,4 @@
`include "csr.hv"
`include "csr.vh"
module csr(
input clk,
input reset,
@@ -249,8 +249,8 @@ module csr(
end
`EUEN_ADDR : euen <= csr_wdata_temp;
`ECFG_ADDR : begin
ecfg <= csr_wdata_temp; // ????????????????
ecfg[ `LIE_1] <= csr_wdata_temp[ `LIE_1];
ecfg[ `LIE_2] <= csr_wdata_temp[ `LIE_2];
end
`ESTAT_ADDR : estat[1:0] <= csr_wdata_temp[1:0];
`ERA_ADDR : era <= csr_wdata_temp;