FPGALab/ddr3_general_design
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UnbalancedCat 5771113897 add axi
2025-03-18 12:11:59 +08:00
ddr_general_design.srcs/sources_1/new
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2025-03-18 12:11:59 +08:00
others
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.gitignore
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ddr_general_design.xpr
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2025-03-18 12:11:59 +08:00
Description
基于 ax7325t 的通用 axi 转 fifo 的 mig ddr3 控制接口项目模板
59 MiB
Languages
Verilog 100%