UnbalancedCat 43f2f61570 something remain

2025-01-13 23:16:02 +08:00

ddr3_general_design.srcs

most logic done (out has some issue, may has plenty of bugs)

2025-01-13 23:15:13 +08:00

others

most logic done (out has some issue, may has plenty of bugs)

2025-01-13 23:15:13 +08:00

.gitignore

first commit

2025-01-06 22:30:12 +08:00

ddr3_general_design.xpr

something remain

2025-01-13 23:16:02 +08:00

Description

基于 ax7325t 的通用 axi 转 fifo 的 mig ddr3 控制接口项目模板

59 MiB

Languages

Verilog 100%