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FPGALab
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ddr3_general_design
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e72b563b6e8825d384af90365010e92bb0b8c3b1
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6 Commits
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UnbalancedCat
e72b563b6e
v1.0
2025-03-24 11:35:28 +08:00
UnbalancedCat
98a79e8c78
sync
2025-03-19 17:32:18 +08:00
UnbalancedCat
cf3f100d53
redo axi construction
2025-03-18 16:56:47 +08:00
UnbalancedCat
5771113897
add axi
2025-03-18 12:11:59 +08:00
UnbalancedCat
5436d507e7
most logic done (out has some issue, may has plenty of bugs)
2025-01-13 23:15:13 +08:00
UnbalancedCat
30fa4e98fe
first commit
2025-01-06 22:30:12 +08:00